AT90PWM81-16MN Atmel, AT90PWM81-16MN Datasheet - Page 14

• Manufacturer Part Number: AT90PWM81-16MN
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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AT90PWM81
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt
flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to exe-
cute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags
can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition
occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remem-
bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt
conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will
be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of
priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored
when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No inter-
rupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
The following example shows how this can be used to avoid interrupts during the timed EEPROM write
sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example
C Code Example
Assembly Code Example
in r16, SREG
cli
sbi EECR, EEMWE
sbi EECR, EEWE
out SREG, r16
char cSREG;
cSREG = SREG;
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG;
sei
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
; set Global Interrupt Enable
; store SREG value
; disable interrupts during timed sequence
; start EEPROM write
; restore SREG value (I-bit)
/* store SREG value */
/* restore SREG value (I-bit) */
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