AT90PWM81-16MN Atmel, AT90PWM81-16MN Datasheet - Page 142

• Manufacturer Part Number: AT90PWM81-16MN
• Description: IC MCU AVR 8K FLASH ISP 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-MLF®, QFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.25.12
12.26 PSC2 Specific Register
12.26.1
142
AT90PWM81
PSC 2 Input Capture Register – PICR2H and PICR2L
PSC 2 Output Matrix – POM2
Table 12-21.
• Bit 7 – PCSTn : PSC Capture Software Trig bit
Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means that the cap-
ture operation was triggered by PCSTn setting otherwise it means that the capture operation was triggered
by a PSC input.
The Input Capture is updated with the PSC counter value each time an event occurs on the enabled PSC
input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit PCAEnx
in PFRCnx register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultane-
ously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte
register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers.
Bit
Read/Write
Initial Value
• Bit 7 – POMV2B3: Output Matrix Output B Ramp 3
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3
• Bit 6 – POMV2B2: Output Matrix Output B Ramp 2
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2
• Bit 5 – POMV2B1: Output Matrix Output B Ramp 1
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1
Bit
Read/Write
Initial Value
PRFMnx3:0
1010b
1011b
1100b
1101b
1110b
1111b
7
POMV2B3
R/W
0
7
PCST2
PICR2[7:0]
R
0
Level Sensitivity and Fault Mode Operation
Description
Reserved (do not use)
PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output
Reserved (do not use)
6
POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2
R/W
0
6
–
R
0
5
R/W
0
5
–
R
0
4
R/W
0
4
–
R
0
3
R/W
0
3
PICR2[11:8]
R
0
2
R/W
0
2
R
0
R/W
1
0
1
R
0
0
R/W
0
0
R
0
7734P–AVR–08/10
PICR2H
PICR2L