ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 43
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ATMEGA8L-8AUR
Manufacturer Part Number
ATMEGA8L-8AUR
Description
MCU AVR 8KB FLASH 8MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8L-8MU.pdf
(302 pages)
Specifications of ATMEGA8L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8AUR
Manufacturer:
Atmel
Quantity:
3 915
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Watchdog Timer
Watchdog Timer
Control Register –
WDTCR
2486Z–AVR–02/11
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega8 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-
lowed when the Watchdog is disabled. Refer to
for details.
Figure 20. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to
3 – WDE: Watchdog Enable” on page
and 2, this bit must also be set when changing the prescaler bits. See the Code Examples on
page
Bit
Read/Write
Initial Value
45.
Table 17 on page
R
7
–
0
CC
OSCILLATOR
= 5V. See characterization data for typical values at other V
WATCHDOG
R
6
–
0
44. The WDR – Watchdog Reset – instruction resets the Watchdog
R
5
–
0
WDCE
R/W
44for a Watchdog disable procedure. In Safety Level 1
4
0
WDE
R/W
“Watchdog Timer Control Register – WDTCR”
3
0
WDP2
R/W
2
0
WDP1
R/W
page
1
0
41.
WDP0
R/W
ATmega8(L)
0
0
WDTCR
CC
levels. By
“Bit
43
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