AT89S52-24JU Atmel, AT89S52-24JU Datasheet - Page 6
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AT89S52-24JU
Manufacturer Part Number
AT89S52-24JU
Description
IC MCU 8K FLASH 24MHZ 44-PLCC
Manufacturer
Atmel
Series
89Sr
Datasheet
1.AT89S52-24AU.pdf
(38 pages)
Specifications of AT89S52-24JU
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89S
Maximum Speed
24 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
UART
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
256 B
Maximum Clock Frequency
33 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
32
Interface
UART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PLCC
Programmable Memory
8K Bytes
Timers
3-16-bit
Voltage, Range
4-5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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4.9
4.10
4.11
4.12
5. Special Function Registers
6
PSEN
EA/VPP
XTAL1
XTAL2
AT89S52
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S52 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to exter-
nal data memory.
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to V
This pin also receives the 12-volt programming enable voltage (V
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in
2) and T2MOD (shown in
Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can
be set for each of the six interrupt sources in the IP register.
5-1.
Table
CC
for internal program executions.
10-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the
PP
) during Flash programming.
1919D–MICRO–6/08
Table 5-