PIC12LC672-04I/SM Microchip Technology, PIC12LC672-04I/SM Datasheet - Page 58

• Manufacturer Part Number: PIC12LC672-04I/SM
• Description: IC MCU OTP 2KX14 LV A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12LC672-04I/SM

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Digital Ic: RoHS Compliant
• Processor Series: PIC12LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: Q732363A

PIC12C67X
9.4
9.4.1
The on-chip POR circuit holds the chip in reset until
V
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to V
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for V
See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, " Power-up Trouble Shooting ."
9.4.2
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows V
level. A configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to V
Table 11-4.
TABLE 9-4:
TABLE 9-5:
Legend: u = unchanged, x = unknown.
DS30561B-page 58
Oscillator Configuration
DD
POR
0
0
0
1
1
1
1
has reached a high enough level for proper opera-
DD
INTRC, EXTRC
, temperature and process variation. See
XT, HS, LP
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
POWER-ON RESET (POR)
POWER-UP TIMER (PWRT)
TO
1
0
x
0
0
u
1
TIME-OUT IN VARIOUS SITUATIONS
STATUS/PCON BITS AND THEIR SIGNIFICANCE
PD
1
x
0
u
0
u
0
DD
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
DD
. This will eliminate exter-
72 ms + 1024T
to rise to an acceptable
PWRTE = 0
72 ms
DD
is specified.
Power-up
OSC
PWRTE = 1
1024T
—
OSC
9.4.3
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
On power-up, the Time-out Sequence is as follows:
first, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary, based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 9-7, Figure 9-8, and Figure 9-9 depict time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-9). This is useful for testing purposes or to
synchronize more than one PIC12C67X device operat-
ing in parallel.
9.4.5
The Power Control/Status Register, PCON (address
8Eh), has one bit. See Register 4-6 for register.
Bit1 is POR (Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise. The user sets
this bit following a Power-on Reset. On subsequent
resets, if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
Wake-up from SLEEP
OSCILLATOR START-UP TIMER (OST)
TIME-OUT SEQUENCE
POWER CONTROL (PCON)/STATUS
REGISTER
1024T
—
OSC
1999 Microchip Technology Inc.