ATMEGA16U2-AU Atmel, ATMEGA16U2-AU Datasheet - Page 214
![MCU AVR 16K FLASH USB 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA16U2-AU
Manufacturer Part Number
ATMEGA16U2-AU
Description
MCU AVR 16K FLASH USB 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16U2-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 214 of 309
- Download datasheet (6Mb)
21.18.8
21.18.9
21.18.10 UECONX – USB Endpoint Control Register
7799D–AVR–11/10
UENUM – USB Endpoint Number Register
UERST – USB Endpoint Reset Register
• Bits 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 2:0 – EPNUM[2:0] Endpoint Number Bits
Writing these bits allows to select the hardware endpoint number that can be accessed by the
CPU interface. This register select the target endpoint number for UECONEX, UECFG0X,
UECFG1X, UESTA0X, UESTA1X, UEINTX, UEIENX, UEDATX, UEBCLX registers. See
point selection” on page 198
• Bits 7:5 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 4:0 – EPRST[4:0]: Endpoint FIFO Reset Bits
Writing this bit to one keeps the selected endpoint (UENUM register value) under reset state.
selected. Writing this bit to zero completes the endpoint reset operation and makes the endpoint
usable. See
• Bits 7:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 5 – STALLRQ: STALL Request Handshake Bit
Writing this bit to one allows the USB controller to generate a STALL answer for the next SETUP
transaction received. This bit is cleared by hardware when the STALL handshake is sent or
when a new SETUP token is received. Writing this bit to zero has no effect. The STALL hand-
shake can be abort using STALLRQC bit.
See
Bit
(0xEB)
Read/Write
Initial Value
Bit
(0xE9)
Read/Write
Initial Value
Bit
(0xEA)
Read/Write
Initial Value
“STALL request” on page 201
“Endpoint reset” on page 197
R
R
7
0
7
0
R
-
-
7
0
-
R
6
0
-
R
R
6
0
6
0
-
-
for more details.
STALLRQ
R/W
R
5
0
-
R
5
0
-
5
0
for more details.
EPRST D4
STALLRQC
R/W
R/W
4
0
R
4
0
for more information.
-
4
0
EPRST D3
RSTDT
ATmega8U2/16U2/32U2
R/W
R/W
3
0
R
3
0
-
3
0
EPRST D2
R/W
R/W
2
0
2
0
R
2
0
-
EPNUM[2:0]
EPRST D1
R/W
R/W
R
1
0
1
0
-
1
0
EPRST D0
EPEN
R/W
R/W
0
0
0
0
R/W
0
0
UECONX
UENUM
UERST
“End-
214
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