PIC12CE673-04I/P Microchip Technology, PIC12CE673-04I/P Datasheet - Page 677
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12CE673-04I/P
Manufacturer Part Number
PIC12CE673-04I/P
Description
IC MCU OTP 1KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE673-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
16Byte
Ram Memory Size
128Byte
Cpu Speed
4MHz
No.
RoHS Compliant
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE673-04I/P
Manufacturer:
Microchip Technology
Quantity:
135
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
- Current page: 677 of 688
- Download datasheet (3Mb)
G
H
1997 Microchip Technology Inc.
GIO
General Input/Output
GPIO
General Purpose Input/Output
GPR
General Purpose Register (RAM). A portion of the data memory that can be used to store the
program’s dynamic variables.
Harvard Architecture
In this architecture the Program Memory and Data Memory buses are separated. This allows
concurrent accesses to Data Memory and Program Memory, which increases the performance
of the device.
Holding Capacitor
This is a capacitor in the Analog to Digital (A/D) module which “holds” to analog input level once
the conversion is started. During acquisition, the holding capacitor is charged/discharged by the
voltage level on the analog input pin. Once the conversion is started, the holding capacitor is dis-
connected from the analog input and “holds” this voltage for the A/D conversion.
HS
High Speed. One of the device oscillator modes. The oscillator circuit is tuned to support the high
frequency operation. Used for operation from 4 MHz to 20 MHz.
Glossary
DS31035A-page 35-5
35
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