PIC16LF1936-I/SS Microchip Technology, PIC16LF1936-I/SS Datasheet
PIC16LF1936-I/SS
Specifications of PIC16LF1936-I/SS
Available stocks
Related parts for PIC16LF1936-I/SS
PIC16LF1936-I/SS Summary of contents
Page 1
... LCD Driver and nanoWatt XLP Technology 2009 Microchip Technology Inc. PIC16F193X/LF193X 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers wtih Preliminary Data Sheet DS41364D ...
Page 2
... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC16F1934 • PIC16F1936 • PIC16F1937 • PIC16F1938 • PIC16F1939 PIC16LF193X Devices: • PIC16LF1933 • PIC16LF1934 • PIC16LF1936 • PIC16LF1937 • PIC16LF1938 • PIC16LF1939 High-Performance RISC CPU: • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed – 32 MHz oscillator/clock input - DC – ...
Page 4
... PIC16F193X/LF193X Family Types PIC16F1933 4096 256 256 PIC16LF1933 PIC16F1934 4096 256 256 PIC16LF1934 PIC16F1936 8192 256 512 PIC16LF1936 PIC16F1937 8192 256 512 PIC16LF1937 PIC16F1938 16384 256 1024 PIC16LF1938 PIC16F1939 16384 256 1024 PIC16LF1939 COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore, Note 1: SEG15 is not available when using 1/4 multiplex displays ...
Page 5
... SEG2/CLKIN/OSC1/RA7 CAP (2) SEG1/V /CLKOUT/OSC2/RA6 (1) P2B /T1CKI/T1OSO/RC0 (1) (1) P2A /CCP2 /T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: 2009 Microchip Technology Inc. PIC16F193X/LF193X PIC16F1933/1936/1938, PIC16LF1933/1936/1938) ( RB7/ICSPDAT/ICDDAT/SEG13 28 1 RB6/ICSPCLK/ICDCLK/SEG14 27 2 RB5/AN13/CPS5/P2B RB4/AN11/CPS4/P1D/COM0 4 RB3/AN9/C12IN2-/CPS3/CCP2 ...
Page 6
... CAP SEG2/CLKIN/OSC1/RA7 (2) SEG1/V /CLKOUT/OSC2/RA6 CAP Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: DS41364D-page 6 PIC16F1933/1936/1938, PIC16LF1933/1936/1938 PIC16F1933/1936/1938 4 18 PIC16LF1933/1936/1938 RC7/RX/DT/P3B/SEG8 15 Preliminary (1) (1) RB3/AN9/C12IN2-/CPS3/CCP2 /P2A /VLCD3 RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 DD SS 2009 Microchip Technology Inc. ...
Page 7
... DD Vss 8, 5, — — — Pin functions can be moved using the APFCON register. Note 1: PIC16F193X devices only. 2: 2009 Microchip Technology Inc. PIC16F193X/LF193X — — — (1) SRNQ (1) — — — — — — — — — — ...
Page 8
... PIC16F193X devices only. 2: DS41364D-page /AN4/RA5 7 34 /AN5/RE0 Preliminary RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 (1) (1) (1) RB5/AN13/CPS5/CCP3 /P3A /T1G /COM1 RB4/AN11/CPS4/COM0 RB3/AN9/C12IN2-/CPS3/CCP2 (1) (1) /P2A /VLCD3 RB2/AN8/CPS2/VLCD2 RB1/AN10/C12IN3-/CPS1/VLCD1 RB0/AN12/CPS0/SRI/INT/SEG0 RD7/CPS15/P1D/SEG20 RD6/CPS14/P1C/SEG19 RD5/CPS13/P1B/SEG18 RD4/CPS12/P2D/SEG17 RC7/RX/DT/SEG8 RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G (1) /SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B (1) 2009 Microchip Technology Inc. ...
Page 9
... Pin Diagram – PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 44-Pin QFN ( 44-pin QFN SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: 2009 Microchip Technology Inc. PIC16F193X/LF193X 1 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN/SEG2 PIC16F1934/1937/1939 PIC16LF1934/1937/1939 7 RE2/AN7/CCP5/SEG23 27 8 RE1/AN6/P3B/SEG22 ...
Page 10
... Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: DS41364D-page RC0/T1OSO/T1CKI/P2B RA6/OSC2/CLKOUT/V 3 RA7/OSC1/CLKIN/SEG2 PIC16F1934/1937/1939 PIC16LF1934/1937/1939 RE2/AN7/CCP5/SEG23 27 7 RE1/AN6/P3B/SEG22 8 26 RE0/AN5/CCP3 RA5/AN4/C2OUT RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 Preliminary (1) (2) /SEG1 CAP (1) (1) /P3A /SEG21 (1) (1) (1) (2) /CPS7/SRNQ /SS /V /SEG5 CAP 2009 Microchip Technology Inc. ...
Page 11
... Vss 12, 6, 6,30, — — — Pin functions can be moved using the APFCON register. Note 1: 2009 Microchip Technology Inc. PIC16F193X/LF193X C12IN0-/ — — (1) SRNQ C2OUT (1) C12IN1- — — — C2IN+/ — — — DACOUT C1IN+ — ...
Page 12
... Appendix A: Data Sheet Revision History.......................................................................................................................................... 495 ® Appendix B: Migrating From Other PIC Devices.............................................................................................................................. 495 Index .................................................................................................................................................................................................. 497 The Microchip Web Site ..................................................................................................................................................................... 505 Customer Change Notification Service .............................................................................................................................................. 505 Customer Support .............................................................................................................................................................................. 505 Reader Response .............................................................................................................................................................................. 506 Product Identification System............................................................................................................................................................. 507 DS41364D-page 12 Preliminary 2009 Microchip Technology Inc. ...
Page 13
... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 13 ...
Page 14
... PIC16F193X/LF193X NOTES: DS41364D-page 14 Preliminary 2009 Microchip Technology Inc. ...
Page 15
... Capture/Compare/PWM Modules ECCP1 ECCP2 ECCP3 CCP4 CCP5 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2009 Microchip Technology Inc. PIC16F193X/LF193X ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
Page 16
... LCD ECCP1 ECCP2 See applicable chapters for more information on peripherals. Note 1: DS41364D-page 16 Program Flash Memory CPU Figure 2-1 Timer1 Timer2 Timer4 Timer6 MSSP ECCP3 CCP4 CCP5 Preliminary EEPROM RAM PORTA PORTB PORTC PORTD PORTE Comparators EUSART 2009 Microchip Technology Inc. ...
Page 17
... Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: PIC16F/LF1933/1936/1938 devices only. 3: PORTD is available on PIC16F/LF1934/1937/1939 devices only. 4: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only. 5: 2009 Microchip Technology Inc. PIC16F193X/LF193X Input Output Type Type TTL CMOS General purpose I/O. AN — ...
Page 18
... Comparator negative input. AN — Capacitive sensing input 3. ST CMOS Capture/Compare/PWM2. — CMOS PWM output. AN — LCD analog input. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2009 Microchip Technology Inc. ...
Page 19
... Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: PIC16F/LF1933/1936/1938 devices only. 3: PORTD is available on PIC16F/LF1934/1937/1939 devices only. 4: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only. 5: 2009 Microchip Technology Inc. PIC16F193X/LF193X Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — ...
Page 20
... LCD analog output. ST CMOS General purpose I/O. AN — Capacitive sensing input 13. — CMOS PWM output. — AN LCD analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2009 Microchip Technology Inc. ...
Page 21
... Pin function is selectable via the APFCON register. Note 1: PIC16F193X devices only. 2: PIC16F/LF1933/1936/1938 devices only. 3: PORTD is available on PIC16F/LF1934/1937/1939 devices only. 4: RE<2:0> are available on PIC16F/LF1934/1937/1939 devices only. 5: 2009 Microchip Technology Inc. PIC16F193X/LF193X Input Output Type Type ST CMOS General purpose I/O. AN — Capacitive sensing input 14. ...
Page 22
... PIC16F193X/LF193X NOTES: DS41364D-page 22 Preliminary 2009 Microchip Technology Inc. ...
Page 23
... Section 3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 “Instruction Set Summary” for more details. 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 23 ...
Page 24
... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W reg Timer Brown-out Reset Preliminary RAM Addr 9 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2009 Microchip Technology Inc. ...
Page 25
... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device / PIC16F1933 PIC16LF1933 / PIC16F1934 PIC16LF1934 / PIC16F1936 PIC16LF1936 / PIC16F1937 PIC16LF1937 / PIC16F1938 PIC16LF1938 / PIC16F1939 PIC16LF1939 2009 Microchip Technology Inc. PIC16F193X/LF193X The following features are associated with access and ...
Page 26
... AND STACK FOR 8KW PARTS PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh 2000h Rollover to Page 0 Rollover to Page 3 7FFFh 2009 Microchip Technology Inc. ...
Page 27
... Page 1 Page 2 Page 3 Page 4 Page 7 Rollover to Page 0 Rollover to Page 7 2009 Microchip Technology Inc. PIC16F193X/LF193X 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in pro- gram memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory ...
Page 28
... STATUS • FSR0 Low • FSR0 High • FSR1 Low • FSR1 High • BSR • WREG • PCLATH • INTCON The core registers are the first 12 Note: addresses of every data memory bank. “Indirect Preliminary 2009 Microchip Technology Inc. ...
Page 29
... Note 1: second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2009 Microchip Technology Inc. PIC16F193X/LF193X For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
Page 30
... Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device Banks PIC16F1933 0-7 PIC16LF1933 8-15 16-23 23-31 PIC16F1934 0-7 PIC16LF1934 8-15 16-23 23-31 PIC16F1936 0-7 PIC16LF1936 8-15 16-23 23-31 PIC16F1937 0-7 PIC16LF1937 8-15 16-23 23-31 PIC16F1938 0-7 PIC16LF1938 8-15 16-23 23-31 PIC16F1939 0-7 PIC16LF1939 ...
Page 31
TABLE 3-3: PIC16F1933/1934 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 32
TABLE 3-4: PIC16F1933/1934 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
Page 33
TABLE 3-5: PIC16F1936/1937 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 34
TABLE 3-6: PIC16F1936/1937 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
Page 35
TABLE 3-7: PIC16F1938/1939 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
Page 36
TABLE 3-8: PIC16F1938/1939 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
Page 37
TABLE 3-9: PIC16F193X/LF193X MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
Page 38
TABLE 3-10: PIC16F193X/LF193X MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
Page 39
... Unimplemented Read as ‘0’ 7EFh = Unimplemented data memory locations, read Legend: as ‘0’. 2009 Microchip Technology Inc. PIC16F193X/LF193X TABLE 3-12: PIC16F1934/1937/1939 MEMORY MAP, BANK 15 Bank 15 LCDCON 791h LCDPS 792h LCDREF 793h LCDCST 794h ...
Page 40
... TOSL FEFh TOSH = Unimplemented data memory locations, read Legend: as ‘0’. 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device Bank( PIC16F193X/LF193X 7 8 9-14 15 16-30 31 DS41364D-page 40 Page No Preliminary 2009 Microchip Technology Inc. ...
Page 41
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 42
... SCS<1:0> 0011 1-00 0011 1-00 LFIOFR HFIOFS 00q0 0q0- qqqq qq0- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 — — 2009 Microchip Technology Inc. ...
Page 43
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 44
... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 2009 Microchip Technology Inc. ...
Page 45
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 46
... STR1B STR1A ---0 0001 ---0 0001 — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 PSS2BD<1:0> 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C5TSEL<1:0> ---- --00 ---- --00 2009 Microchip Technology Inc. ...
Page 47
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 48
... IOCBP1 IOCBP0 0000 0000 0000 0000 IOCBN1 IOCBN0 0000 0000 0000 0000 IOCBF1 IOCBF0 0000 0000 0000 0000 — — — — — — — — — — — — — — — — — — 2009 Microchip Technology Inc. ...
Page 49
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 50
... INTF IOCIF 0000 000x 0000 000u — — 2009 Microchip Technology Inc. ...
Page 51
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 52
... COM2 COM2 SEG17 SEG16 xxxx xxxx uuuu uuuu COM2 COM2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM3 COM3 SEG9 SEG8 xxxx xxxx uuuu uuuu COM3 COM3 SEG17 SEG16 xxxx xxxx uuuu uuuu COM3 COM3 — — 2009 Microchip Technology Inc. ...
Page 53
... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. 3: The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices. 4: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 54
... Microchip Technology Inc. ...
Page 55
... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). 2009 Microchip Technology Inc. PIC16F193X/LF193X 3.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables ...
Page 56
... TOSH/TOSL registers will return ‘0’. If 0x06 the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will 0x05 return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 0x1F 0x0000 STKPTR = 0x1F Preliminary Stack Reset Disabled (STVREN = 0) Stack Reset Enabled (STVREN = 1) 2009 Microchip Technology Inc. ...
Page 57
... FIGURE 3-7: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-8: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2009 Microchip Technology Inc. PIC16F193X/LF193X 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 ...
Page 58
... Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x10 Preliminary 2009 Microchip Technology Inc. ...
Page 59
... FIGURE 3-10: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: 2009 Microchip Technology Inc. PIC16F193X/LF193X 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
Page 60
... TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 DS41364D-page 60 Indirect Addressing 0 7 FSRxH Bank Select 0001 0010 1111 Bank 31 Preliminary 0 7 FSRxL 0 Location Select 2009 Microchip Technology Inc. ...
Page 61
... FSRnL Location Select 0x2000 0x29AF 2009 Microchip Technology Inc. PIC16F193X/LF193X 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
Page 62
... PIC16F193X/LF193X NOTES: DS41364D-page 62 Preliminary 2009 Microchip Technology Inc. ...
Page 63
... Configuration Word 2 registers, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 8007h and Configuration Word 2 register at 8008h. 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 63 ...
Page 64
... Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit pin function is MCLR; Weak pull-up enabled. pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2009 Microchip Technology Inc. ...
Page 65
... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3: 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 65 ...
Page 66
... FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control 8 kW Flash memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only Write protection off 10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control ...
Page 67
... See Section 4.5 “Device ID and Revision ID” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16193X/PIC16LF193X Memory Specification” (DS41360). 2009 Microchip Technology Inc. PIC16F193X/LF193X “Write such as Programming Preliminary ...
Page 68
... PIC16F1933 100011010 = PIC16F1934 100011011 = PIC16F1936 100011100 = PIC16F1937 100011101 = PIC16F1938 100011110 = PIC16F1939 100100001 = PIC16LF1933 100100010 = PIC16LF1934 100100011 = PIC16LF1936 100100100 = PIC16LF1937 100100101 = PIC16LF1938 100100110 = PIC16LF1939 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: ...
Page 69
... MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) 2009 Microchip Technology Inc. PIC16F193X/LF193X The oscillator module can be configured in one of six clock modes – External clock – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
Page 70
... Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Preliminary ® MCU design is fully EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN ® PIC MCU OSC2/CLKOUT (1) 2009 Microchip Technology Inc. ...
Page 71
... AN849, “Basic PIC Oscillator Design” (DS00849) ® • AN943, “Practical PIC Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) 2009 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 5- Internal Logic Sleep C2 Ceramic Resonator Note 1: A series resistor (R ceramic resonators with low drive level ...
Page 72
... PIC MCU OSC1/CLKIN Internal Clock OSC2/CLKOUT (1) 100 k, <3V EXT 3 k R 100 k, 3-5V EXT C > 20 pF, 2-5V EXT Output depends upon CLKOUTEN bit of the Configuration Word 1. ) and capacitor (C ) values EXT EXT 2009 Microchip Technology Inc. ...
Page 73
... OSCTUNE register (Register 5-3). 3. The (Low-Frequency LFINTOSC Oscillator) is uncalibrated and operates at 31 kHz. 2009 Microchip Technology Inc. PIC16F193X/LF193X 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). ...
Page 74
... These dupli- cate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. Preliminary 2009 Microchip Technology Inc. ...
Page 75
... PLLEN Configuration Word ‘1’. However, the 4X PLL cannot be disabled by software and the 8 MHz HFINTOSC option will no longer be available. 2009 Microchip Technology Inc. PIC16F193X/LF193X 5.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF< ...
Page 76
... LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock DS41364D-page 76 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary Running Running Running 2009 Microchip Technology Inc. ...
Page 77
... Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the Timer1 Oscillator. 2009 Microchip Technology Inc. PIC16F193X/LF193X 5.3.3 TIMER1 OSCILLATOR The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...
Page 78
... MHz (1) (1) 31.25 kHz-500 kHz (1) 31.25 kHz-16 MHz (1) 31 kHz 32 kHz 16-32 MHz Preliminary Oscillator Delay Oscillator Warm-up Delay (T ) WARM 2 cycles 1 cycle of each 1024 Clock Cycles (OST) 2 s (approx.) 1 cycle of each 1024 Clock Cycles (OST (approx.) 2009 Microchip Technology Inc. ...
Page 79
... OSC1 1022 1023 0 1 OSC2 Program Counter System Clock 2009 Microchip Technology Inc. PIC16F193X/LF193X 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC< ...
Page 80
... Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. Preliminary 2009 Microchip Technology Inc. ...
Page 81
... Clock Output Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. 2009 Microchip Technology Inc. PIC16F193X/LF193X Oscillator Failure Test Test Preliminary Failure ...
Page 82
... Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: DS41364D-page 82 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0 2009 Microchip Technology Inc. ...
Page 83
... LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate 2009 Microchip Technology Inc. PIC16F193X/LF193X R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘ ...
Page 84
... Preliminary R/W-0/0 R/W-0/0 bit 0 Register Bit 1 Bit 0 on Page SCS<1:0> 82 LFIOFR HFIOFS 83 84 (1) — CCP2IE 101 (1) — CCP2IF 104 — TMR1ON 201 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> CPD 64 FOSC<2:0> STVREN PLLEN 66 — WRT<1:0> 2009 Microchip Technology Inc. ...
Page 85
... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2009 Microchip Technology Inc. PIC16F193X/LF193X PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41364D-page 85 ...
Page 86
... BOR protection is unchanged by Sleep. DD Preliminary falls below V for a DD BOR , the device BORDC Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2009 Microchip Technology Inc. ...
Page 87
... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2009 Microchip Technology Inc. PIC16F193X/LF193X T BORRDY BOR Protection Active (1) T PWRT < T ...
Page 88
... Power-up Timer and oscillator start- up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 6- 4). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary Timer configuration. See 2009 Microchip Technology Inc. ...
Page 89
... FIGURE 6-4: RESET START-UP SEQUENCE V DD Internal POR Power Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2009 Microchip Technology Inc. PIC16F193X/LF193X T PWRT T MCLR T OST Preliminary DS41364D-page 89 ...
Page 90
... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2009 Microchip Technology Inc. ...
Page 91
... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2009 Microchip Technology Inc. PIC16F193X/LF193X U-0 R/W/HC-1/q R/W/HC-1/q — ...
Page 92
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41364D-page 92 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 87 POR BOR SWDTEN 113 2009 Microchip Technology Inc. ...
Page 93
... A block diagram of the interrupt logic is shown in Figure 7-1 and Figure 7-2. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 7-2) 2009 Microchip Technology Inc. PIC16F193X/LF193X Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE ...
Page 94
... CCP5IF CCP5IE OSFIF OSFIE TMR1IF TMR1IE TMR6IF TMR6IE C2IF C2IE C1IF C1IE EEIF EEIE BCLIF BCLIE LCDIF LCDIE DS41364D-page 94 Preliminary 2009 Microchip Technology Inc. To Interrupt Logic (Figure 7-1) ...
Page 95
... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2009 Microchip Technology Inc. PIC16F193X/LF193X 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 96
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2009 Microchip Technology Inc. ...
Page 97
... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2009 Microchip Technology Inc. PIC16F193X/LF193X Q2 Q3 ...
Page 98
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41364D-page 98 Preliminary 2009 Microchip Technology Inc. ...
Page 99
... The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state 2009 Microchip Technology Inc. PIC16F193X/LF193X Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 100
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2009 Microchip Technology Inc. ...
Page 101
... Disables the LCD module interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 102
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0 2009 Microchip Technology Inc. ...
Page 103
... Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2009 Microchip Technology Inc. PIC16F193X/LF193X Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 104
... R/W-0/0 R/W-0/0 R/W-0/0 EEIF BCLIF LCDIF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the U-0 R/W-0/0 — CCP2IF bit 0 2009 Microchip Technology Inc. ...
Page 105
... TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC16F193X/LF193X Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 106
... C1IF EEIF BCLIF LCDIF CCP4IF CCP3IF TMR6IF — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 99 PS<2:0> 191 TMR2IE TMR1IE 100 — CCP2IE 101 TMR4IE — 102 TMR2IF TMR1IF 103 — CCP2IF 104 TMR4IF — 105 2009 Microchip Technology Inc. ...
Page 107
... Shaded cells are not used by LDO. Legend: PIC16F193X only. Note 1: 2009 Microchip Technology Inc. PIC16F193X/LF193X On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...
Page 108
... PIC16F193X/LF193X NOTES: DS41364D-page 108 Preliminary 2009 Microchip Technology Inc. ...
Page 109
... See Section 16.0 “Digital-to-Analog Con- verter (DAC) Module” and Section 14.0 “Fixed Volt- age Reference (FVR)” for more information on these modules. 2009 Microchip Technology Inc. PIC16F193X/LF193X 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 110
... Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 99 IOCBF1 IOCBF0 150 IOCBN1 IOCBN0 150 IOCBP1 IOCBP0 150 TMR2IE TMR1IE 100 — CCP2IE 101 TMR4IE — 102 TMR2IF TMR1IF 103 — CCP2IF 104 TMR4IF — 105 SWDTEN 113 2009 Microchip Technology Inc. ...
Page 111
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2009 Microchip Technology Inc. PIC16F193X/LF193X 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41364D-page 111 ...
Page 112
... STATUS register are changed to indicate the event. See Active Section 3.0 “Memory Organization” and STATUS Active register (Register 3-1) for more information. Disabled Active Disabled Disabled Preliminary WDT Cleared Cleared until the end of OST Unaffected 2009 Microchip Technology Inc. ...
Page 113
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 114
... PIC16F193X/LF193X NOTES: DS41364D-page 114 Preliminary 2009 Microchip Technology Inc. ...
Page 115
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2009 Microchip Technology Inc. PIC16F193X/LF193X 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 116
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2009 Microchip Technology Inc. ...
Page 117
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2009 Microchip Technology Inc. PIC16F193X/LF193X EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 118
... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Latches/ Boundary 8 words, 000 Preliminary instruction on the next 2009 Microchip Technology Inc. ...
Page 119
... NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 119 ...
Page 120
... Example 11-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. The code Note: Example 11-5 must be repeated multiple times to fully program an erased program memory row. Preliminary 2009 Microchip Technology Inc. sequence provided in ...
Page 121
... EEADRL<2:0> = 000 EEADRL<2:0> = 001 Buffer Register 2009 Microchip Technology Inc. PIC16F193X/LF193X continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 122
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2009 Microchip Technology Inc. ...
Page 123
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2009 Microchip Technology Inc. PIC16F193X/LF193X ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 124
... Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EED- ATL register pair is cleared. Function Read Access User IDs Yes Yes Yes Preliminary Write Access Yes No No 2009 Microchip Technology Inc. ...
Page 125
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 125 ...
Page 126
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2009 Microchip Technology Inc. ...
Page 127
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 128
... EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCLIE LCDIE C1IF EEIF BCLIF LCDIF Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page WR RD 127 115* 126 126 126 126 INTF IOCIF 99 — CCP2IE 101 — CCP2IF 104 2009 Microchip Technology Inc. ...
Page 129
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2009 Microchip Technology Inc. PIC16F193X/LF193X 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 12-1 ...
Page 130
... CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3 DS41364D-page 130 R/W-0/0 R/W-0/0 R/W-0/0 P2BSEL SRNQSEL C2OUTSEL U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets CAP CAP Preliminary R/W-0/0 R/W-0/0 SSSEL CCP2SEL bit 0 CAP CAP CAP CAP 2009 Microchip Technology Inc. ...
Page 131
... MOVLW B'11110000' ;Set RA<7:4> as inputs MOVWF TRISA ;and set RA<3:0> as ;outputs 2009 Microchip Technology Inc. PIC16F193X/LF193X 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet ...
Page 132
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2009 Microchip Technology Inc. ...
Page 133
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-1/1 R/W-1/1 ...
Page 134
... SE1 SE0 333 SE9 SE8 333 PS<2:0> 191 RA1 RA0 132 SRPS SRPR 185 SSPxM<3:0> 285 TRISA1 TRISA0 132 Register Bit 10/2 Bit 9/1 Bit 8/0 on Page BOREN<1:0> CPD 64 FOSC<2:0> BORV STVREN PLLEN 66 — WRT<1:0> 2009 Microchip Technology Inc. ...
Page 135
... The interrupt-on-change feature is disabled on a Power-on Reset. Reference “Interrupt-On-Change” for more information. 2009 Microchip Technology Inc. PIC16F193X/LF193X 12.3.3 ANSELB REGISTER The ANSELB register (Register 12-9) is used to configure the Input mode of an I/O pin to analog. ...
Page 136
... RB6 RB7 1. ICSPDAT (Programming) 2. ICDDAT (enabled by Configuration Word) 3. SEG13 (LCD) 4. RB7 R/W-x/u R/W-x/u R/W-x/u RB4 RB3 RB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u RB1 RB0 bit 0 2009 Microchip Technology Inc. ...
Page 137
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-1/1 R/W-1/1 ...
Page 138
... IOCBN1 IOCBN0 150 IOCBF1 IOCBF0 150 LATB2 LATB1 LATB0 137 LMUX<1:0> 329 SE2 SE1 SE0 333 SE10 SE9 SE8 333 PS<2:0> 191 RB2 RB1 RB0 136 T1GSS<1:0> 202 TRISB2 TRISB1 TRISB0 137 WPUB2 WPUB1 WPUB0 138 2009 Microchip Technology Inc. ...
Page 139
... TRISC ; MOVLW B'11110000' ;Set RC<7:4> as inputs MOVWF TRISC ;and set RC<3:0> as ;outputs 2009 Microchip Technology Inc. PIC16F193X/LF193X 12.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The is TRISC pins, their combined functions and their output priorities are briefly described here ...
Page 140
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0 2009 Microchip Technology Inc. ...
Page 141
... SMP CKE T1CON TMR1CS<1:0> TXSTA CSRC TX9 TRISC TRISC7 TRISC6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 T1GSEL P2BSEL SRNQSEL C2OUTSEL DCxB<1:0> CCPxM<3:0> LATC5 ...
Page 142
... RD1 RD2 1. P2B (CCP) 2. RD2 RD3 1. SEG16 (LCD) 2. P2C (CCP) 3. RD3 RD4 1. SEG17 (LCD) 2. P2D (CCP) 3. RD4 RD5 1. SEG18 (LCD) 2. P1B (CCP) 3. RD5 RD6 1. SEG19 (LCD) 2. P1C (CCP) 3. RD6 RD7 1. SEG20 (LCD) 2. P1D (CCP) 3. RD7 Preliminary 2009 Microchip Technology Inc. ...
Page 143
... LATD<7:0>: PORTD Output Latch Value bits Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is Note 1: return of actual I/O pin values. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 2: 2009 Microchip Technology Inc. PIC16F193X/LF193X (1) R/W-x/u R/W-x/u R/W-x/u RD4 ...
Page 144
... TRISD4 TRISD3 TRISD2 Preliminary (2) R/W-1/1 R/W-1/1 ANSD1 ANSD0 bit 0 (1) Register on Bit 1 Bit 0 Page ANSD1 ANSD0 144 231 CPSOUT T0XCS 323 324 LATD1 LATD0 143 LMUX<1:0> 329 SE17 SE16 333 RD1 RD0 143 TRISD1 TRISD0 143 2009 Microchip Technology Inc. ...
Page 145
... MOVLW B‘00001100’ ;Set RE<3:2> as inputs MOVWF TRISE ;and set RE<1:0> ;as outputs 2009 Microchip Technology Inc. PIC16F193X/LF193X 12.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet ...
Page 146
... Value at POR and BOR/Value at all other Resets (1) U-0 R-1 R/W-1 (1) TRISE3 TRISE2 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u (1) (1) RE1 RE0 bit 0 R/W-1 R/W-1 (1) (1) TRISE1 TRISE0 bit 0 2009 Microchip Technology Inc. ...
Page 147
... When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. ANSELE register is not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as ‘0’ 2: 2009 Microchip Technology Inc. PIC16F193X/LF193X U-0 R/W-x/u R/W-x/u ...
Page 148
... U-0 U-0 — — — bit 0 (1) Register Bit 1 Bit 0 on Page 161 GO/DONE ADON ANSE1 ANSE0 147 231 LATE1 LATE0 147 LMUX<1:0> 329 SE17 SE16 333 RE1 RE0 146 TRISE1 TRISE0 146 — — 148 2009 Microchip Technology Inc. ...
Page 149
... R RBx IOCBPx 2009 Microchip Technology Inc. PIC16F193X/LF193X 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 150
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2009 Microchip Technology Inc. ...
Page 151
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE ...
Page 152
... PIC16F193X/LF193X NOTES: DS41364D-page 152 Preliminary 2009 Microchip Technology Inc. ...
Page 153
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2009 Microchip Technology Inc. PIC16F193X/LF193X 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 154
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition ( Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR<1:0> Preliminary R/W-0/0 R/W-0/0 ADFVR<1:0> bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR<1:0> 154 2009 Microchip Technology Inc. ...
Page 155
... AN13 DAC FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: Not available on PIC16F/LF1933/1936/1938. 2009 Microchip Technology Inc. PIC16F193X/LF193X The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) ...
Page 156
... Section 29.0 “Electrical Specifications” for more information. Table 15-1 gives examples of appropriate ADC clock selections. Unless using the F Note: system clock frequency will change the ADC clock adversely affect the ADC result. Preliminary 2009 Microchip Technology Inc. AD specifica any changes in the RC frequency, which may ...
Page 157
... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2009 Microchip Technology Inc. PIC16F193X/LF193X ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 158
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2009 Microchip Technology Inc. ...
Page 159
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2009 Microchip Technology Inc. PIC16F193X/LF193X 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 160
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2009 Microchip Technology Inc. ...
Page 161
... See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information. Note 1: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. 2: Not available on the PIC16F/LF1933/1936/1938. 3: 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ ...
Page 162
... V REF connected to internal fixed voltage reference REF DS41364D-page 162 R/W-0/0 U-0 R/W-0/0 — ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS - REF DD + REF Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 2009 Microchip Technology Inc. ...
Page 163
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 164
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2009 Microchip Technology Inc. ...
Page 165
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2009 Microchip Technology Inc. PIC16F193X/LF193X source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 166
... V - REF DS41364D-page 166 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale V + REF Transition Preliminary HOLD REF Sampling Switch (k) 2009 Microchip Technology Inc. ...
Page 167
... FVRRDY DACCON0 DACEN DACLPS DACCON1 — — unknown unchanged, — = unimplemented read as ‘0’ value depends on condition. Shaded cells are not Legend: used for ADC module. 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — ADNREF ANSA5 ANSA4 ...
Page 168
... PIC16F193X/LF193X NOTES: DS41364D-page 168 Preliminary 2009 Microchip Technology Inc. ...
Page 169
... Either the positive voltage source, (V negative voltage source can be disabled. SRC 2009 Microchip Technology Inc. PIC16F193X/LF193X The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source ...
Page 170
... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41364D-page 170 Digital-to-Analog Converter (DAC SRC Steps SRC + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator and ADC Modules) DACOUT DACOE Buffered DAC Output 2009 Microchip Technology Inc. ...
Page 171
... Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2009 Microchip Technology Inc. PIC16F193X/LF193X Preliminary DS41364D-page 171 ...
Page 172
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 DACR<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets 5 -))*(DACR<4:0>/( SRC Preliminary U-0 R/W-0/0 --- DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0 2009 Microchip Technology Inc. ...
Page 173
... FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC Module. Legend: 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR<1:0> DACOE — DACPSS<1:0> ...
Page 174
... PIC16F193X/LF193X NOTES: DS41364D-page 174 Preliminary 2009 Microchip Technology Inc. ...
Page 175
... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2009 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 17-1: SINGLE COMPARATOR – V ...
Page 176
... Output of comparator can be frozen during debugging. 3: DS41364D-page 176 (1) Interrupt Interrupt C POL ( CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2009 Microchip Technology Inc. ...
Page 177
... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2009 Microchip Technology Inc. PIC16F193X/LF193X 17.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register ...
Page 178
... See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 16.0 “Digital-to-Analog (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. Preliminary Converter 2009 Microchip Technology Inc. ...
Page 179
... Analog Voltage Threshold Voltage T Note 1: See Section 29.0 “Electrical Specifications” 2009 Microchip Technology Inc. PIC16F193X/LF193X 17.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 17-3. Since the analog input pins share their connection with a digital input, they have reverse ...
Page 180
... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. DS41364D-page 180 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0 2009 Microchip Technology Inc. ...
Page 181
... Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 182
... C2HYS C2SYNC 180 C1NCH<1:0> 181 C2NCH<1:0> 181 MC2OUT MC1OUT 181 ADFVR<1:0> 154 — DACNSS 172 172 INTF IOCIF 99 — CCP2IE 101 — CCP2IF 104 TRISA1 TRISA0 132 TRISB1 TRISB0 137 ANSA1 ANSA0 133 ANSB1 ANSB0 137 2009 Microchip Technology Inc. ...
Page 183
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2009 Microchip Technology Inc. PIC16F193X/LF193X 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 184
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41364D-page 184 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2009 Microchip Technology Inc. SRQ SRNQ ...
Page 185
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input. Set only, always reads back ‘ 0 ’. Note 1: 2009 Microchip Technology Inc. PIC16F193X/LF193X MHz MHz OSC OSC 39 ...
Page 186
... C1 Comparator output has no effect on the reset input of the SR Latch DS41364D-page 186 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2009 Microchip Technology Inc. ...
Page 187
... SRCON0 SRLEN SRCLK<2:0> SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR Latch module. 2009 Microchip Technology Inc. PIC16F193X/LF193X Bit 5 Bit 4 Bit 3 Bit 2 ANSA5 ANSA4 ANSA3 ANSA2 SRQEN SRNQEN ...
Page 188
... PIC16F193X/LF193X NOTES: DS41364D-page 188 Preliminary 2009 Microchip Technology Inc. ...
Page 189
... From CPSCLK 1 TMR0CS TMR0SE T0XCS 2009 Microchip Technology Inc. PIC16F193X/LF193X When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register can Note: be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...
Page 190
... Section 29.0 “Electrical Specifications”. 19.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41364D-page 190 Preliminary 2009 Microchip Technology Inc. ...
Page 191
... Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936 devices. Note 1: 2009 Microchip Technology Inc. PIC16F193X/LF193X R/W-1/1 R/W-1/1 R/W-1/1 ...
Page 192
... PIC16F193X/LF193X NOTES: DS41364D-page 192 Preliminary 2009 Microchip Technology Inc. ...
Page 193
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2009 Microchip Technology Inc. PIC16F193X/LF193X • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 20 block diagram of the Timer1 module ...
Page 194
... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2009 Microchip Technology Inc. ...
Page 195
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2009 Microchip Technology Inc. PIC16F193X/LF193X 20.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 196
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary 2009 Microchip Technology Inc. ...
Page 197
... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2009 Microchip Technology Inc. PIC16F193X/LF193X Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. ...
Page 198
... PIC16F193X/LF193X FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 20-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41364D-page 198 Preliminary 2009 Microchip Technology Inc ...
Page 199
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF 2009 Microchip Technology Inc. PIC16F193X/LF193X Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41364D-page 199 ...
Page 200
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41364D-page 200 Set by hardware on falling edge of T1GVAL Preliminary 2009 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...