ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 54

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.6
9.3.7
54
ATtiny88 Automotive
PCMSK3 – Pin Change Mask Register 3
PCMSK2 – Pin Change Mask Register 2
• Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3..0 – PCINT27..24: Pin Change Enable Mask 27..24
Each PCINT27..24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT27..24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT27..24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16
Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PCINT23
R/W
R
7
0
7
0
-
PCINT22
R/W
R
6
0
6
0
-
PCINT21
R/W
R
5
0
5
0
-
PCINT20
R/W
R
4
0
4
0
-
PCINT27
PCINT19
R/W
R/W
3
0
3
0
PCINT26
PCINT18
R/W
R/W
2
0
2
0
PCINT25
PCINT17
R/W
R/W
1
0
1
0
PCINT24
PCINT16
R/W
R/W
0
0
0
0
9157B–AVR–01/10
PCMSK3
PCMSK2