ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 59

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.5
9157B–AVR–01/10
Reading the Pin Value
Table 10-1
Table 10-1.
Note:
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay.
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
DDxn
0
0
0
1
1
INSTRUCTIONS
1. Or port-wise PUDx bit in PORTCR register.
SYSTEM CLK
SYNC LATCH
Figure
PORTxn
summarizes the control signals for the pin value.
Port Pin Configurations
0
1
1
0
1
10-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
r17
(in MCUCR)
PUD
X
X
X
0
1
Figure
(1)
XXX
10-2, the PINxn Register bit and the preceding latch con-
Output
Output
Input
Input
Input
I/O
pd,max
t
pd, max
and t
Pull-up Comment
0x00
Yes
No
No
No
No
XXX
pd,min
t
ATtiny88 Automotive
pd, min
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
respectively.
Figure 10-4
in r17, PINx
shows a timing dia-
0xFF
59