PIC16F887-E/P Microchip Technology, PIC16F887-E/P Datasheet - Page 222

• Manufacturer Part Number: PIC16F887-E/P
• Description: IC PIC MCU FLASH 8KX14 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F887-E/P

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 35
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/USART
• On-chip Adc: 14-chx10-bit
• Number Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 368 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53273-916
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD
• Lead Free Status / Rohs Status: Details

PIC16F882/883/884/886/887
14.3
The
interrupt sources:
• External Interrupt RB0/INT
• Timer0 Overflow Interrupt
• PORTB Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• Enhanced CCP Interrupt
• EUSART Receive and Transmit Interrupts
• Ultra Low-Power Wake-up Interrupt
• MSSP Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON, PIE1 and PIE2 registers, respectively. GIE is
cleared on Reset.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the INT-
CON register:
• INT Pin Interrupt
• PORTB Change Interrupts
• Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the PIR1
and PIR2 registers. The corresponding interrupt enable
bits are contained in PIE1 and PIE2 registers.
The following interrupt flags are contained in the PIR1
register:
• A/D Interrupt
• EUSART Receive and Transmit Interrupts
• Timer1 Overflow Interrupt
• Synchronous Serial Port (SSP) Interrupt
• Enhanced CCP1 Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
DS41291F-page 220
PIC16F882/883/884/886/887
Interrupts
has
multiple
The following interrupt flags are contained in the PIR2
register:
• Fail-Safe Clock Monitor Interrupt
• 2 Comparator Interrupts
• EEPROM Data Write Interrupt
• Ultra Low-Power Wake-up Interrupt
• CCP2 Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
For external interrupt events, such as the INT pin,
PORTB change interrupts, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 14-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For
comparators, A/D, data EEPROM, EUSART, MSSP or
Enhanced CCP modules, refer to the respective
peripheral section.
14.3.1
External interrupt on RB0/INT pin is edge-triggered;
either rising if the INTEDG bit (OPTION_REG<6>) is
set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from Sleep, if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up
(0004h). See Section 14.6 “Power-Down Mode
(Sleep)” for details on Sleep and Figure 14-10 for
timing of wake-up from Sleep through RB0/INT
interrupt.
Note 1: Individual interrupt flag bits are set,
additional
2: When an instruction that clears the GIE
RB0/INT INTERRUPT
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
information
© 2009 Microchip Technology Inc.
of
the
on
status
Timer1,
of
Timer2,
their