ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 186
ATA6616-P3QW
Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6616-P3QW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL
Quantity:
950
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.16
4.16.1
4.16.2
186
LIN/UART - Local Interconnect Network Controller or UART
Atmel ATA6616/ATA6617
LIN Features
UART Features
Table 4-47.
The LIN (Local Interconnect Network) is a serial communications protocol which efficiently
supports the control of mechatronics nodes in distributed automotive applications. The main
properties of the LIN bus are:
•
•
•
•
•
•
LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN
are not required. The specification of the line driver/receiver needs to match the ISO9141
NRZ-standard.
If LIN is not required, the controller alternatively can be programmed as Universal Asynchro-
nous serial Receiver and Transmitter (UART).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single master with multiple slaves concept
Low cost silicon implementation based on common UART/SCI interface
Self synchronization with on-chip oscillator in slave node
Deterministic signal transmission with signal propagation time computable in advance
Low cost single-wire implementation
Speed up to 20Kbit/s.
Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility)
Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow
Concept” of LIN 2.1 Specification
Automatic LIN Header Handling and Filtering of Irrelevant LIN Frames
Automatic LIN Response Handling
Extended LIN Error Detection and Signaling
Hardware Frame Time-out Detection
“Break-in-data” Support Capability
Automatic Re-synchronization to Ensure Proper Frame Integrity
Fully Flexible Extended Frames Support Capabilities
Full Duplex Operation (Independent Serial Receive and Transmit Processes)
Asynchronous Operation
High Resolution Baud Rate Generator
Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames
Data Over-Run and Framing Error Detection
0
1
USIPOS
(Alternate)
(Default)
Port A
PortB
USI Pin Position
USI Pin Position
DI, SDA
DO
USCK, SCL
DI, SDA
DO
USCK, SCL
PB0 - (PCINT8/OC1AU)
PB1 - (PCINT9/OC1BU)
PB2 - (PCINT10/OC1AV)
PA4 - (PCINT4/ADC4/ICP1/MOSI)
PA2 - (PCINT2/ADC2/OC0A/MISO)
PA5 - (PCINT5/ADC5/T1/SCK)
9132D–AUTO–12/10
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