ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 234
ATA6616-P3QW
Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6616-P3QW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL
Quantity:
950
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.18.12.5
4.18.12.6
234
Atmel ATA6616/ATA6617
DIDR0 – Digital Input Disable Register 0
DIDR1 – Digital Input Disable Register 1
• Bits 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When
an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to
zero when DIDR1 register is written.
• Bits 6..4 – ADC10D..ADC8D: ADC10..8 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When
an analog signal is applied to the ADC10:8 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
• Bits 3:0 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be writ-
ten to zero when DIDR1 is written.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADC7D /
AIN1D
R/W
R
7
0
7
0
-
ADC6D /
ADC10D
AIN0D
R/W
R/W
6
0
6
0
ADC5D
ADC9D
R/W
R/W
5
0
5
0
ADC4D
ADC8D
R/W
R/W
4
0
4
0
ADC3D
R/W
R
3
0
3
0
-
ADC2D
R/W
R
2
0
2
0
-
ADC1D
R/W
R
1
0
1
0
-
ADC0D DIDR0
R/W
R
0
0
0
0
9132D–AUTO–12/10
-
DIDR1
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