ATTINY44A-MU Atmel, ATTINY44A-MU Datasheet - Page 24

• Manufacturer Part Number: ATTINY44A-MU
• Description: IC MCU AVR 4K FLASH 20MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 20-ch x 10-bit
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 20
• Height: 0.74 mm
• Length: 4 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 4 mm
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Clock System
6.1
6.1.1
24
Clock Subsystems
ATtiny24A/44A/84A
CPU Clock – clk
Figure 6-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 6-1.
The clock subsystems are detailed in the sections below.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
CPU
ADC
External Clock
presents the principal clock systems in the AVR and their distribution. All of the clocks
clk
clk
ADC
I/O
Clock Distribution
Source clock
General I/O
System Clock
Modules
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
Calibrated RC
Oscillator
Oscillator
Crystal
33.
Reset Logic
CPU Core
clk
clk
CPU
FLASH
Crystal Oscillator
Low-Frequency
Watchdog Timer
Watchdog clock
RAM
Watchdog
Oscillator
Flash and
EEPROM
“Power Manage-
Calibrated RC
Oscillator
8183C–AVR–03/11