ATTINY44-15SSZ Atmel, ATTINY44-15SSZ Datasheet
ATTINY44-15SSZ
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ATTINY44-15SSZ Summary of contents
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... SOIC, 20-pin QFN/MLF: Twelve Programmable I/O Lines • Operating Voltage: – 2.7 - 5.5V for Atmel ATtiny24/44/84 • Speed Grade – Atmel ATtiny24/44/84 8MHz @ 2.7 - 5.5V 16MHz @ 4.5 - 5.5V • Automotive Temperature Range • Low Power Consumption – Active Mode: 1MHz, 2.7V: 800µ ...
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... Disclaimer Typical values contained in this data sheet are based on simulations and characterization of actual Atmel ATtiny24/44/84 AVR microcontrollers manufactured on the typical process tech- nology. Applicable Automotive Min. and Max. values will be available after devices representative of the whole process excursion (corner run) have been characterized. ...
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... Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATtiny24/44/84 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. VCC GND 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ® ...
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... ISP flash allows the program memory to be re-programmed in-system through an SPI serial interface conventional non-volatile memory programmer on-chip boot code running on the AVR core. The Atmel ATtiny24/44/84 AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
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... RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the Atmel listed on 2.3.4 RESET Reset input ...
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... Resources A comprehensive set of development tools, driver and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part-specific header file is included before compilation ...
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... CPU Core 5.1 Overview This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1. In order to maximize performance and parallelism, the AVR separate memories and buses for program and data ...
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... AVR architecture. The memory spaces in the Atmel A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table ...
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... The zero flag Z indicates a zero result in an arithmetic or logic operation. See the instruction set summary for detailed information. • Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the instruction set summary for detailed information. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary ...
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... General Purpose Register File The register file is optimized for the Atmel achieve the required performance and flexibility, the following input/output schemes are sup- ported by the register file: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • ...
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... AVR this case, the SPH register will not be present. 5.6.1 SPH and SPL – Stack Pointer High and Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D) ...
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... Reset and Interrupt Handling The Atmel AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written with a logical one together with the global interrupt enable bit in the status register in order to enable the interrupt ...
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... If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the Atmel® AVR® exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. ...
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... C Code Example 5.8.1 Interrupt Response Time The interrupt execution response for all the enabled Atmel cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock-cycle period, the program counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles ...
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... Since all AVR instructions are bits wide, the flash mem- ory is organized as 1024/2048/4096 x 16. The flash memory has an endurance of at least 10,000 write/erase cycles. The Atmel ATtiny24/44/84 program counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 program memory locations. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and 128/256/512 bytes of internal data SRAM in the Atmel modes. The Register File is described in Figure 6-2. ...
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... But because the erase and write operations are split possible to do the erase operations when the system allows time-crit- ical operations to be done (typically after power-up). 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ® ATtiny24/44/84 contains 128/256/512 bytes of EEPROM data memory orga- “Preventing EEPROM Corruption” on page 20 “ ...
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... The following code examples show one assembly function and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Atmel ATtiny24/44/84 [Preliminary] 18 32. “Oscillator Calibration Register – OSCCAL” on ...
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... Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } The code examples are only valid for addressing mode. ® Atmel Atmel ATtiny24 and ATtiny44, using 8-bit 19 ...
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... Set up address register */ EEARL = ucAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; } The code examples are only valid for addressing mode. ® Atmel Atmel ATtiny24 and ATtiny44, using 8-bit reset protection CC 7701E–AVR–02/11 ...
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... The I/O space definition of the Atmel page All Atmel ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 6.5.4 EECR – EEPROM Control Register Bit 0x1C (0x3C) Read/Write Initial Value Atmel ATtiny24/44/84 [Preliminary – – ...
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... Bit 7 – Res: Reserved Bit This bit is reserved for future use, and will always read Atmel compatibility with future AVR mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the Atmel ATtiny24/44/84 and will always read as zero. ...
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... GPIOR2 – General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value 6.5.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x14 (0x34) Read/Write Initial Value 6.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write Initial Value Atmel ATtiny24/44/84 [Preliminary MSB R/W R/W R/W R ...
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... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] presents the principal clock systems in the AVR Clock Distribution General I/O ADC ...
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... This gives more accurate ADC conversion results. 7.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the Atmel routed to the appropriate modules. Table 7-1. Device Clocking Option External Clock Calibrated Internal RC Oscillator 8 ...
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... Table 7-3. CKSEL3..1 100 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 7-4 on page 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Table 7-3 on page Crystal Oscillator Connections 27. Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 101 0 ...
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... C1 and C2. When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table Table 7-5. SUT1.. Notes: Atmel ATtiny24/44/84 [Preliminary] 28 Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and SUT1..0 Power-save ( ...
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... To drive the device from an external clock source, CLKI should be driven as shown in 7-3 on page grammed to “0000”. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] and “Internal Oscillator Speed” on page 204 7-6. If selected, it will operate with no external components. During reset, hardware Table 22-2 on page 180 ...
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... MCU is kept in reset during such changes in the clock frequency. Note that the system clock prescaler can be used to implement run-time changes of the inter- nal clock frequency while still ensuring stable operation. See page 31 Atmel ATtiny24/44/84 [Preliminary] 30 External Clock Drive Configuration EXTERNAL CLOCK SIGNAL 30 ...
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... In this interval, twp active clock edges are produced. Here the previous clock period, and T2 is the period corresponding to the new prescaler setting. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 31. Start-up Times for the 128kHz Internal Oscillator Start-up Time from ...
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... CLKPCE bit. • Bits 6..4 – Res: Reserved Bits These bits are reserved bits in the Atmel • Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal sys- tem clock ...
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... CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-10. CLKPS3 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Clock Prescaler Select CLKPS2 CLKPS1 ...
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... FLASH Atmel ATtiny24/44/84 [Preliminary] 34 ® ® AVR provides various sleep modes allowing the user to tailor the power presents the different clock systems in the Atmel Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains (2) 1. For INT0, only level interrupt. ...
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... Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] , while allowing the other clocks to run. for details 164), the BOD is actively monitoring the supply voltage during a sleep period. In some level has dropped during the sleep period ...
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... Otherwise, the internal voltage reference will be enabled, independent of sleep mode. See figure the Analog Comparator. Atmel ATtiny24/44/84 [Preliminary] 36 “Power-down Supply Current” on page 194 ® ...
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... Digital Input Disable Register (DIDR0). See “DIDR0 – Digital Input Disable Register 0” on page 155 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] for details on the start-up time. “Watchdog Timer” on page 44 for details on how to configure the Watchdog ...
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... These bits select between the three available sleep modes as shown in Table 8-2. Note: • Bit 2 – BODSE: BOD Sleep Enable The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence. Atmel ATtiny24/44/84 [Preliminary BODS ...
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... Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut- down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary – ...
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... Fuses. The different selections for the delay period are presented in 26. 9.2 Reset Sources The Atmel ATtiny24/44/84 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. • ...
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... RESET after V decreases below the detection level. Figure 9-2. V TIME-OUT INTERNAL 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Reset Logic Power-on Reset Circuit Brown-out BODLEVEL [1..0] Reset Circuit Pull-up Resistor ...
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... Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V its positive edge, the delay counter starts the MCU after the Time-out period – t expired. Atmel ATtiny24/44/84 [Preliminary] 42 MCU Start-up, RESET Extended Externally V ...
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... Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t “Watchdog Timer” on page 44 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] External Reset During Operation ...
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... The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten dif- ferent clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the Atmel ATtiny24/44/84 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to The Wathdog Timer can also be configured to generate an interrupt instead of a reset ...
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... Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] WDT Configuration as a Function of the Fuse Settings of WDTON Safety ...
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... Bit 6 – WDIE: Watchdog Timeout Interrupt Enable When this bit is written to logical one, WDE is cleared, and the I-bit in the status register is set, the watchdog time-out interrupt is enabled. In this mode the corresponding interrupt is exe- cuted instead of a reset if a time-out in the watchdog timer occurs. Atmel ATtiny24/44/84 [Preliminary ...
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... Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 9-4 on page 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Watchdog Timer Configuration WDIE Watchdog Timer State 0 0 ...
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... Table 9-4. WDP3 Atmel ATtiny24/44/84 [Preliminary] 48 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 Typical Time-out at Cycles cycles 16ms 4K cycles 32ms 8K cycles 64ms 16K cycles 0.125s 32K cycles 0.25s 64K cycles 0.5s 128K cycles 1.0s 256K cycles 2.0s 512K cycles 4 ...
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... WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example C Code Example Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] (1) WDT_off: WDR ; Clear WDRF in MCUSR ldi r16, (0<<WDRF) ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATtiny24/44/84. For a general explanation of the AVR Interrupt Handling” on page 10.1 Interrupt Vectors Table 10-1. Vector No. Atmel ATtiny24/44/84 [Preliminary] 50 12. Reset and Interrupt Vectors Program Address Source 1 0x0000 RESET 2 0x0001 ...
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... If the program never enables an interrupt source, the Interrupt Vectors are not used, and regu- lar program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel Address Labels Code 0x0000 0x0001 ...
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... The start-up time is defined by the SUT and CKSEL fuses as described in 11.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 11-1. Timing of pin change interrupts Atmel ATtiny24/44/84 [Preliminary] 52 “Clock Systems and their Distribution” on page “System Clock and Clock Options” on page pin_lat pcint_in_(0) ...
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... Any change on any enabled PCINT11..8 pin will cause an inter- rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT11..8 pins are enabled individually by the PCMSK1 Register. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary ...
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... Alternatively, the flag can be cleared by writing a logical one to it. 11.2.4 PCMSK1 – Pin Change Mask Register 1 Bit 0x20 (0x40) Read/Write Initial Value • Bits 7, 4– Res: Reserved Bits These bits are reserved bits in the Atmel Atmel ATtiny24/44/84 [Preliminary – ...
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... Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set (logical one) and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the cor- responding I/O pin is disabled. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary ...
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... Using the I/O port as General Digital I/O is described in 57. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page alternate functions. Atmel ATtiny24/44/84 [Preliminary] 56 ® ® AVR ports have true read-modify-write functionality when used as general digital 56 ...
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... To switch the pull-up resistor off, PORTxn has to be written logical zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] (1) Pxn SLEEP ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. on page 59 pin value. The maximum and minimum propagation delays are denoted t respectively. Atmel ATtiny24/44/84 [Preliminary] 58 summarizes the control signals for the pin value. Port Pin Configurations PUD ...
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... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in positive edge of the clock. In this case, the delay t clock period. Figure 12-4. Synchronization when Reading a Software Assigned Pin Value 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn ...
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... CC SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by vari- ous other alternate functions as described in Atmel ATtiny24/44/84 [Preliminary] 60 (1) ... ; Define pull-ups and set outputs high ...
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... Most port pins have alternate functions in addition to being general digital I/Os. page 62 be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the Atmel microcontroller family. 7701E–AVR–02/11 ...
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... Figure 12-5. Alternate Port Functions Note: Table 12-2 on page 63 indexes from signals are generated internally in the modules having the alternate function. Atmel ATtiny24/44/84 [Preliminary] 62 PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn 0 DIEOExn DIEOVxn 1 0 SLEEP PUOExn: Pxn PULL-UP OVERRIDE ENABLE ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for fur- ther details. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Generic Description of Overriding Signals for Alternate Functions Full Name Description ...
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... AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change interrupt 0. Atmel ATtiny24/44/84 [Preliminary] 64 Port A Pins Alternate Functions Port Pin Alternate Function ADC0: ADC input channel 0 ...
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... The OC1B pin is also the output pin for the PWM mode timer function. PCINT5: Pin change interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary ...
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... Table 12-4 on page 66 overriding signals shown in Table 12-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Atmel ATtiny24/44/84 [Preliminary Table 12-6 on page 67 Figure 12-5 on page Overriding Signals for Alternate Functions in PA7..PA5 PA7/ADC7/OC0B/ICP1/ PA6/ADC6/DI/SDA/OC1A/ PCINT7 PCINT6 USIWM1 0 (SDA + PORTA6) • ...
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... DIEOV DI AIO Table 12-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Overriding Signals for Alternate Functions in PA4..PA2 PA4/ADC4/USCK/SCL/T1/ PCINT4 PA3/ADC3/T0/PCINT3 USIWM1 0 USI_SCL_HOLD + 0 PORTA4) • ADC4D USIWM1 • ADC4D USI_PTOE ...
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... CKOUT fuse is programmed, regardless of the PORTB2 and DDB2 settings. It will also be output during reset. PCINT10: Pin change interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. Atmel ATtiny24/44/84 [Preliminary] 68 Port B Pins Alternate Functions Port Pin Alternate Function XTAL1: Crystal Oscillator Input ...
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... Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] and Table 12-9 on page 70 Figure 12-5 on page Overriding Signals for Alternate Functions in PB3..PB2 RESET/dW/ PB3/ PCINT11 (1) RSTDISBL + DEBUGWIRE_ENABLE 1 (1) RSTDISBL + DEBUGWIRE_ENABLE (2) DEBUGWIRE_ENABLE • ...
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... DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 57 12.4.2 PORTA – Port A Data Register Bit 0x1B (0x3B) Read/Write Initial Value Atmel ATtiny24/44/84 [Preliminary] 70 Overriding Signals for Alternate Functions in PB1..PB0 PB1/XTAL2/PCINT9 (1) EXT_OSC 0 (1) EXT_OSC ...
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... Initial Value 12.4.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 12.4.7 PINB – Port BInput Pins Address Bit 0x16 (0x36) Read/Write Initial Value 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary DDA7 DDA6 DDA5 DDA4 R/W R/W R/W R/W 0 ...
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... TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Atmel ATtiny24/44/84 [Preliminary] 72 Figure 1-1 on page “ ...
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... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. ure 13-2 on page 73 Figure 13-2. Counter Unit Block Diagram 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary “Output Compare Unit” on page 74 Table 13-1 on page 73 are also used extensively throughout the document. ...
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... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. See 77. Figure 13-3 on page 75 Atmel ATtiny24/44/84 [Preliminary] 74 count Increment or decrement TCNT0 by 1. direction Select between increment and decrement ...
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... All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] DATA BUS OCRnx = (8-bit Comparator ) ...
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... The data direction register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is vis- ible on the pin. The port override function is independent of the waveform generation mode. Atmel ATtiny24/44/84 [Preliminary] 76 COMnx1 ...
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... This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] “Register Description” on page 84 84, and for phase correct PWM refer to “Modes of Operation” on page ...
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... TCNT0 and OCR0x, and set at bottom. In inverting compare output mode, the output is set on compare match and cleared at bottom. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. Atmel ATtiny24/44/84 [Preliminary when OCR0A is set to zero (0x00) ...
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... TCNT0, and clearing (or setting) the OC0x register at the timer clock cycle when the coun- ter is cleared (changes from top to bottom). The PWM frequency for the output can be calculated by the following equation: f OCnxPWM The variable N represents the prescale factor (1, 8, 64, 256, or 1024).. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Figure 13-6 on page TCNTn OCn OCn Period 1 ...
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... The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT0 slopes rep- resent compare matches between OCR0x and TCNT0. Atmel ATtiny24/44/84 [Preliminary] 80 Figure 13-7 on page 81. The TCNT0 value is in the timing diagram, which when OCR0A is set to zero ...
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... PWM mode. For inverted PWM, the output will have the opposite logic values. At the very start of period 2 in even though there is no compare match. The point of this transition is to guarantee symmetry around bottom. There are two cases that give a transition without a compare match. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary Table 13-4 on page ...
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... Figure 13-8. Timer/Counter Timing Diagram, no Prescaling (clk TCNTn Figure 13-9 on page 82 Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f (clk TCNTn Figure 13-10 on page 83 except CTC mode and PWM mode, where OCR0A is TOP. Atmel ATtiny24/44/84 [Preliminary] 82 Figure 13-8 on page 82 clk I/O clk Tn /1) I/O ...
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... OCRnx Figure 13-11 on page 83 and fast PWM mode where OCR0A is TOP. Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with (clk TCNTn (CTC) OCRnx 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] clk I/O clk Tn /8) I/O OCRnx - 1 OCFnx shows the setting of OCF0A and the clearing of TCNT0 in CTC mode ...
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... When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 13-2. COM01 Table 13-3 on page 84 to fast PWM mode. Table 13-3. COM01 Note: Atmel ATtiny24/44/84 [Preliminary COM0A1 COM0A0 COM0B1 R/W R/W ...
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... Table 13-5. COM01 Table 13-3 on page 84 to fast PWM mode. Table 13-6. COM01 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] shows the COM0A1:0 bit functionality when the WGM02:0 bits are set Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 0 Normal port operation, OC0A disconnected. ...
Page 86
... Note: Atmel ATtiny24/44/84 [Preliminary special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 78 for more details. shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase ...
Page 87
... These bits are reserved bits in the ATtiny24/44/84, and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary FOC0A FOC0B – ...
Page 88
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. Atmel ATtiny24/44/84 [Preliminary] 88 Clock Select Bit Description CS01 CS00 Description ...
Page 89
... OCR0A, the output compare register 0 A. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logi- cal one to the flag. When the I-bit in SREG, OCIE0A (timer/counter 0 compare match interrupt enable), and OCF0A are set, the timer/counter 0 compare match interrupt is executed. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary – ...
Page 90
... When the SREG I-bit, TOIE0 (timer/counter 0 overflow inter- rupt enable), and TOV0 are set, the timer/counter 0 overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. See and “Waveform Generation Mode Bit Description” on page Atmel ATtiny24/44/84 [Preliminary] 90 Table 13-8 on page 86 86. 7701E–AVR–02/11 ...
Page 91
... I/O pins, refer to accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-spe- cific I/O Register and bit locations are listed in the 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ® “Pinout Atmel ATtiny24/44/84” on page “ ...
Page 92
... T1 pin. The clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. The timer/counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk Atmel ATtiny24/44/84 [Preliminary] 92 Count Clear ...
Page 93
... The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 100. The compare match event will also set the compare match 134). The input capture unit includes a digital filtering unit (noise The counter reaches the BOTTOM when it becomes 0x0000. ...
Page 94
... Accessing 16-bit Registers TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the Atmel CPU via the 8-bit data bus. The 16-bit registers must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storage of the high byte of the 16-bit access ...
Page 95
... Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] (1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ...
Page 96
... The timer/counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the timer/counter control register B (TCCR1B). For details on clock sources and prescaler, see Atmel ATtiny24/44/84 [Preliminary] 96 (1) TIM16_WriteTCNT1: ...
Page 97
... For more details about advanced counting sequences and waveform generation, see 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Figure 14-2 on page 97 shows a block diagram of the counter and its surroundings. DATA BUS ...
Page 98
... When the low byte is read, the high byte is cop- ied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location, it will access the TEMP register. Atmel ATtiny24/44/84 [Preliminary] 98 DATA BUS ...
Page 99
... Using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation is not recommended. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 94. (Figure 15-1 on page “Accessing 16-bit Regis- 120). The edge detector is also ...
Page 100
... The elements of the block diagram that are not directly a part of the output compare unit are shaded gray. Figure 14-4. Output Compare Unit, Block Diagram Atmel ATtiny24/44/84 [Preliminary] 100 (“Modes of Operation” on page 103). ...
Page 101
... The easiest way of setting the OC1x value is to use the force output com- pare (1x) strobe bits in normal mode. The OC1x register keeps its value even when changing between waveform generation modes. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 94. “Accessing 16-bit Regis- 101 ...
Page 102
... The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See The COM1x1:0 bits have no effect on the Input Capture unit. Atmel ATtiny24/44/84 [Preliminary] 102 COMnx1 Waveform ...
Page 103
... OCR1A or ICR1 define the top value for the counter, and hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Table 14-1 on page 113, and for phase correct and phase and frequency correct PWM refer to 114. ...
Page 104
... The fast pulse width modulation, or fast PWM, mode (WGM13 14, or 15) provides a high-frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from bottom to top then restarts from bottom. Atmel ATtiny24/44/84 [Preliminary] 104 when OCR1A is set to zero (0x0000) ...
Page 105
... OCR1A or ICR1 is used for defining the top value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] R FPWM 105. The figure shows fast PWM mode when OCR1A or ICR1 is used to define top. ...
Page 106
... OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The wave- form generated will have a maximum frequency of (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. Atmel ATtiny24/44/84 [Preliminary] 106 f clk_I/O ...
Page 107
... The small horizontal lines on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 14-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] TOP log R = ---------------------------------- - PCPWM log 107 ...
Page 108
... TCNT1 and OCR1x while up-counting, and set on the compare match while down-counting. Atmel ATtiny24/44/84 [Preliminary] 108 114). The actual OC1x value will only be visible on the port pin if the data direction for ...
Page 109
... ICR1 is used for defining the top value, the OC1A or ICF1 flag is set accordingly when TCNT1 has reached top. The interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] and Figure 14-9 on page 109). ...
Page 110
... OCR1x register is updated with the OCR1x buffer value (only for modes utilizing double buffering). setting of OCF1x. Atmel ATtiny24/44/84 [Preliminary] 110 shows, the output generated is, in contrast to the phase correct 114). The actual OC1x value will only be visible on the port pin if the data ...
Page 111
... PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] clk I/O clk Tn ...
Page 112
... Figure 14-12. Timer/Counter Timing Diagram, no Prescaling Figure 14-13 on page 112 Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f Atmel ATtiny24/44/84 [Preliminary] 112 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn ...
Page 113
... WGM13:0 bit settings. when the WGM13:0 bits are set to a normal or CTC mode (non-PWM). Table 14-1. COM1A1/COM1B1 Table 14-2 on page 113 to the fast PWM mode. Table 14-2. COM1A1/COM1B1 Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary COM1A1 COM1A0 COM1B1 R/W R/W R/W ...
Page 114
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see ation” on page Atmel ATtiny24/44/84 [Preliminary] 114 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase ...
Page 115
... When a capture is triggered according to the ICES1 setting, the counter value is copied into the input capture register (ICR1). The event will also set the input capture flag (ICF1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] (1) WGM11 WGM10 ...
Page 116
... FOC1A/FOC1B bit, an immediate compare match is forced on the waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bit settings. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore the value present in the COM1x1:0 bits that determine the effect of the forced compare. Atmel ATtiny24/44/84 [Preliminary] 116 and Figure 14-11 ...
Page 117
... The output compare registers are 16 bits in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary ...
Page 118
... TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to logical one and the I-flag in the status register is set (interrupts glob- ally enabled), the timer/counter 1 overflow interrupt is enabled. The corresponding interrupt vector (see Atmel ATtiny24/44/84 [Preliminary] 118 ...
Page 119
... TOV1 flag is set when the timer overflows. See behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the timer/counter 1 overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logical one to its bit location. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary – ...
Page 120
... Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise there is a risk that a false timer/counter clock pulse could be generated. Atmel ATtiny24/44/84 [Preliminary] 120 ). Alternatively, one of four taps from the prescaler can be ...
Page 121
... Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n When this bit is set to one, the timer/counter n prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] < f /2) given a 50/50 duty cycle. Because the edge detector ExtClk clk_I/O /2 ...
Page 122
... A transparent latch is inserted between the serial register output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the data input (DI) pin independent of the configuration. Atmel ATtiny24/44/84 [Preliminary] 122 ® “Pinout Atmel ATtiny24/44/84” ...
Page 123
... The counter overflow (interrupt) flag, or USIOIF, can therefore be used to deter- mine when a transfer is completed. The clock is generated by the master device software by toggling the USCK pin via the PORT register writing a logical one to the USITC bit in USICR. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Bit7 Bit6 Bit5 Bit4 ...
Page 124
... The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor set to idle mode. Depending on the protocol used, the slave device can now set its out- put to high impedance. Atmel ATtiny24/44/84 [Preliminary] 124 ( Reference ) 1 ...
Page 125
... The fourth and fifth instructions set the three-wire mode, positive edge shift register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as an SPI master with maximum speed (f SPITransfer_Fast: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] out USIDR,r16 ldi r16,(1<<USIOIF) out ...
Page 126
... Note that the first two instructions are for initialization only and need only to be executed once. These instructions set the three-wire mode and positive edge shift register clock. The loop is repeated until the USI counter overflow flag is set. Atmel ATtiny24/44/84 [Preliminary] 126 out ...
Page 127
... The master generates clock by the by toggling the USCK pin via the PORT register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Bit7 Bit6 Bit5 Bit4 ...
Page 128
... If the slave is not able to receive more data, it does not acknowledge the data byte it has last received. When the master does a read operation, it must terminate the operation by forcing the acknowledge bit low after the last byte is transmitted. Figure 16-6. Start Condition Detector, Logic Diagram Atmel ATtiny24/44/84 [Preliminary] 128 SDA SCL ...
Page 129
... Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Figure 16-6 on page “Clock Systems and their Distribution” on page for further details. /4. This is also the maximum data transmit and CK 128 ...
Page 130
... When two-wire mode is selected, the USISIF flag is set (one) when a start condition is detected. When output disable mode or three-wire mode is selected and (USICSx = 0b11 and USICLK = 0) or (USICS = 0b10 and USICLK = 0), any edge on the SCK pin sets the flag. Atmel ATtiny24/44/84 [Preliminary] 130 7 ...
Page 131
... USICR – USI Control Register Bit 0x0D (0x2D) Read/Write Initial Value The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary USISIE USIOIE USIWM1 USIWM0 R/W ...
Page 132
... The counter and shift register can, therefore, be clocked externally, and data input sampled, even when outputs are disabled. The relation between USIWM1..0 and USI operation is summarized in Table 16-1. USIWM1 Note: Atmel ATtiny24/44/84 [Preliminary] 132 Relations between USIWM1..0 and the USI Operation USIWM0 Description 0 0 Outputs, clock hold, and start detector disabled ...
Page 133
... USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] shows the relationship between the USICS1..0 and USICLK settings Relations between the USICS1..0 and USICLK Setting ...
Page 134
... ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the analog comparator, as shown in 17-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input of the analog comparator. Atmel ATtiny24/44/84 [Preliminary] 134 Figure 17-1 on page 134. ...
Page 135
... When this bit is cleared, AIN0 is applied to the positive input of the analog comparator. • Bit 5 – ACO: Analog Comparator Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of one to two clock cycles. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Analog Comparator Multiplexed Input ADEN MUX4.. ...
Page 136
... PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logical one to reduce power consumption in the digital input buffer. Atmel ATtiny24/44/84 [Preliminary] 136 Table 17-2 ...
Page 137
... And internal reference voltage of nominally 1.1V is provided on chip. Alternatively, VCC can be used as reference voltage for single-ended channels. There is also an option to use an external voltage reference and turn off the internal voltage reference. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ADC Input Voltage Range CC ® ...
Page 138
... ADC. For differential measurements, all adjacent analog inputs can be selected as an input pair. Every input can also be measured with ADC3. These pairs of differ- ential inputs are measured by the ADC through the differential gain amplifier. Atmel ATtiny24/44/84 [Preliminary] 138 ADTS2...ADTS0 8-BIT DATA BUS ADC CTRL. & ...
Page 139
... Note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in SREG is cleared. A conver- sion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event . 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 139 ...
Page 140
... If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. Atmel ATtiny24/44/84 [Preliminary] 140 ADTS[2:0] ADIF SOURCE 1 ...
Page 141
... Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Figure 18-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 142 MUX and REFS Update Sample & Hold ...
Page 142
... Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL Figure 18-7. ADC Timing Diagram, Free Running Conversion Table 18-1. Condition First conversion Normal conversions Auto Triggered conversions Atmel ATtiny24/44/84 [Preliminary] 142 Sample & Prescaler Hold Reset MUX and REFS Update ...
Page 143
... V as either V after switching the reference voltage source may be inaccurate, and the user is advised to dis- card this result. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ) indicates the conversion range for the ADC. Sin- REF will result in codes close to 0x3FF. V REF , internal 1 ...
Page 144
... Signal components higher than the Nyquist frequency (f distortion from unpredictable signal convolution. The user is advised to remove high-frequency components with a low-pass filter before applying the signals as inputs to the ADC. Atmel ATtiny24/44/84 [Preliminary] 144 mode must be selected and the ADC conversion complete interrupt must be enabled ...
Page 145
... The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior: • Offset Error: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5LSB). Ideal value: 0LSB. Figure 18-9. Offset Error 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary ADCn I IL the analog ground plane, and keep them well away from high-speed switching digi- tal tracks ...
Page 146
... Figure 18-11. Integral Non-linearity (INL) • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB. Atmel ATtiny24/44/84 [Preliminary] 146 Output Code Output Code Gain ...
Page 147
... The result is presented in one-sided form, from 0x3FF to 0x000. 18.8.2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is where V and V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Output Code 0x3FF 1 LSB 0x000 0 ADC is the voltage on the selected input pin and V ...
Page 148
... EEPROM for each chip as a part of the production test. The software calibration can be done utilizing the formula: where ADCn are the ADC data registers fixed coefficient and T sensor offset value determined and stored into EEPROM as a part of the production test. Atmel ATtiny24/44/84 [Preliminary] 148 V POS ...
Page 149
... Selecting the single-ended channel ADC8 enables the temperature measurement. See are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary REFS1 ...
Page 150
... For offset calibration purposes, the offset of certain differential channels can be measured by selecting the same input for both negative and positive input. This calibration can be done for ADC0, ADC3, and ADC7. detailed manner. Atmel ATtiny24/44/84 [Preliminary] 150 Single Ended Input Channel Selections. Single Ended Input ...
Page 151
... Table 18-5. Positive Differential 1. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Differential Input channel Selections. Negative Differential Input Input ADC0 (PA0) ADC0 (PA0) ADC1 (PA1) ADC3 (PA3) ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC0 (PA0) ...
Page 152
... When this bit is written to logical one and the I-bit in SREG is set, the ADC conversion com- plete interrupt is activated. • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 18-6. Atmel ATtiny24/44/84 [Preliminary] 152 ADEN ...
Page 153
... If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in on page 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ADC Prescaler Selections (Continued) ADPS2 ADPS1 1 0 ...
Page 154
... See “ADCSRB – ADC Control and Status Register B” on page • Bit 5 – Res: Reserved Bit This bit is reserved bit in the Atmel® ATtiny24/44/84, and will always read as what was written there. • Bit 4 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. ...
Page 155
... ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logical one to reduce power consumption in the digital input buffer. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ADC Auto Trigger Source Selections ADTS2 ADTS1 ...
Page 156
... Figure 19-1. The debugWIRE Setup Figure 19-1 on page 156 and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. Atmel ATtiny24/44/84 [Preliminary] 156 ® instructions in the CPU and to program the different non-volatile ...
Page 157
... All external reset sources must be disconnected. 19.4 Software Break Points debugWIRE supports program memory break points by the Atmel Setting a break point in AVR Studio The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the program memory. ...
Page 158
... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. Atmel ATtiny24/44/84 [Preliminary] 158 7701E–AVR–02/11 ...
Page 159
... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Because this instruction addresses the flash byte-by-byte, the LSB (bit Z0) of the Z-pointer is also used. Figure 20-1. Addressing the Flash During SPM Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary Z15 Z14 ...
Page 160
... Flash program corruption can occur for two reasons when the voltage is too low. First, a regu- lar write sequence to the flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the supply voltage is too low. Atmel ATtiny24/44/84 [Preliminary] 160 7 ...
Page 161
... Flash corru ptio asily b e avoided by fo llowing at lea st one the se d esig n recommendations: 1. Keep the Atmel voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low V tion circuit can be used reset occurs while a write operation is in progress, the write operation will be completed provided the power supply voltage is sufficient ...
Page 162
... SPM instruction SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remains high until the operation is completed. Writing any combination other than "10001", "01001", "00101", "00011", or "00001" in the lower five bits will have no effect. Atmel ATtiny24/44/84 [Preliminary] 162 7701E–AVR–02/11 ...
Page 163
... Memory Programming This section describes the different methods for programming the Atmel memories. 21.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (set to one) or can be programmed (set to zero) to obtain the additional security listed in The lock bits can only be erased to one with the chip erase command ...
Page 164
... Fuse High Byte RSTDISBL DWEN SPIEN WDTON EESAVE BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes: Atmel ATtiny24/44/84 [Preliminary] 164 ® ATtiny24/44/84 has three fuse bytes. describe briefly the functionality of all the fuses and how they are mapped into the Fuse Extended Byte Bit No Description 7 - ...
Page 165
... The three bytes reside in a separate address space. For the Atmel ATtiny24/44/84, the signature bytes are given in Table 21-6. Device ATtiny24 ATtiny44 ATtiny84 21.4 Calibration Byte The signature area of the Atmel ATtiny24/44/84 has one byte of calibration data for the inter- nal RC oscillator ...
Page 166
... Page Size Table 21-7. Device ATtiny24 ATtiny44 ATtiny84 Table 21-8. Device ATtiny24 ATtiny44 ATtiny84 Atmel ATtiny24/44/84 [Preliminary] 166 No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size PCWORD 1K words 16 words PC[3:0] (2K bytes) 2K words 32 words PC[4:0] (4K bytes) ...
Page 167
... Depending on the CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f High: > 2 CPU clock cycles for f 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] MOSI MISO SCK RESET GND 1 ...
Page 168
... Serial Programming Algorithm When writing serial data to the Atmel edge of SCK. When reading data from the Atmel ATtiny24/44/84, data are clocked on the falling edge of SCK. See To program and verify the Atmel ATtiny24/44/84 in the serial programming mode, the following sequence is recommended (see four-byte instruction formats in 1 ...
Page 169
... Read Extended Fuse Bits Read Calibration Byte (6) Write Instructions Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) Write Lock bits 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] power off. CC and Figure 21-2 on page 170 Byte 1 Byte 2 $AC $53 ...
Page 170
... Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘ ...
Page 171
... High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the Atmel Figure 21-3. High-voltage Serial Programming Table 21-12. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode SDI ...
Page 172
... High-voltage Serial Programming Algorithm To program and verify the Atmel ming mode, the following sequence is recommended (see instruction formats in on page 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between V 2. Set RESET pin to “ ...
Page 173
... Repeat 2 and 3 until the entire flash is programmed, or until all data has been programmed. 5. End page programming by loading "No Operation" command. When writing or reading serial data to the Atmel ing edge of the serial clock. See 22-9 on page 186 Figure 21-4. Addressing the Flash which is Organized in Pages 7701E– ...
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... Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in on page 21.8.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V Atmel ATtiny24/44/84 [Preliminary] 174 Table 21-15 on page 175): gramming cycle to finish ...
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... Page Buffer SDI 0_0000_0000_00 SII 0_0110_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Program EEPROM SII 0_0110_0100_00 Page SDO x_xxxx_xxxx_xx 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Instruction Format Instr.2/6 Instr.3/7 0_0000_0000_00 0_0000_0000_00 0_0110_0100_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0000_0000_00 0_0010_1100_00 0_0110_1101_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_0000_00 ...
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... SDI 0_0000_1000_00 Read Calibration SII 0_0100_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Load “No Operation” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx Atmel ATtiny24/44/84 [Preliminary] 176 Instruction Format Instr.2/6 Instr.3/7 0_aaaa_aaaa_00 0_eeee_eeee_00 0_0001_1100_00 0_0010_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_aaaa_aaaa_00 0_0000_0000_00 0_0001_1100_00 0_0110_1000_00 ...
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... The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] 177 ...
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... Current I/O Pin Input Leakage I IHPORTB Current I/O Pin Input Leakage I ILPORTB Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor pu Atmel ATtiny24/44/84 [Preliminary] 178 *NOTICE: +0.5V CC (1) ....................... ±5.0mA T = -40°C to 125° 2.7V to 5.5V (unless otherwise noted Condition Min ...
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... ACLK Leakage Current Notes: 1. All DC Characteristics contained in this data sheet are based on actual silicon characterization of Atmel ATtiny24/44/84 AVR microcontrollers manufactured in corner run process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual Automotive silicon. 2. “Max” means the highest value where the pin is guaranteed to be read as low. ...
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... CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL t Change in period from one clock cycle to the next CLCL Atmel ATtiny24/44/84 [Preliminary] 180 2.7V - 5.5V 2.7V - 5.5V 1. The overall jitter increase proportionally to the divider ratio V IH1 Temperature 25°C -40°C - 125°C -40° ...
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... Bandgap reference start-up time BG I Bandgap reference current consumption BG Notes: 1. Values are guidelines only. 2. This is the limit to which VDD can be lowered without losing RAM data Table 22-5. Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Condition ( 2.7V 2.7V 2.7V BODLEVEL Fuse Coding BODLEVEL [2 ...
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... Gain Error Offset Error Conversion Time Clock Frequency Vref External Voltage Reference V Input Voltage IN V Internal Voltage Reference INT R Analog Input Resistance AIN Atmel ATtiny24/44/84 [Preliminary] 182 Condition Min Single-ended conversion Single-ended conversion 4V, REF CC ADC clock = 200kHz Single-ended conversion V = 4V, V ...
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... Table 22-7. ADC Characteristics, Differential Channels, T Symbol Parameter Resolution TUE Absolute Accuracy INL Integral Non-Linearity (INL) DNL Differential Non-linearity (DNL) Gain Error 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] = -40°C to 125°C A Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200kHz ...
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... Reference Voltage REF V Input Voltage IN V Input Differential Voltage DIFF 22.6 Serial Programming Characteristics Figure 22-3. Serial Programming Timing Figure 22-4. Serial Programming Waveforms Atmel ATtiny24/44/84 [Preliminary] 184 = -40°C to 125°C (Continued) A Condition Gain = 4V, V REF CC ADC clock = 50 - 200kHz Bipolar - Gain = 20x ...
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... Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Serial Programming Characteristics, T (Unless Otherwise Noted) Parameter Oscillator Frequency (Atmel ATtiny24/44/84V) CLCL Oscillator Period (Atmel ATtiny24/44/84V) Oscillator Frequency (ATtiny24/44/84, V CLCL 5.5V) Oscillator Period (ATtiny24/44/84, V 5.5V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High ...
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... High-voltage Serial Programming Characteristics Figure 22-5. High-voltage Serial Programming Timing Table 22-9. Symbol WLWH_PFB Atmel ATtiny24/44/84 [Preliminary] 186 CC CK High-voltage Serial Programming Characteristics T = 25°C ± 10 5.0V ± 10% (Unless otherwise noted Parameter SCI (PB0) Pulse Width High SHSL SCI (PB0) Pulse Width Low ...
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... Power-down mode with Watchdog Timer disabled represents the differential cur- rent drawn by the Watchdog Timer. 23.1 Active Supply Current Figure 23-1. Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) - Temp.=25°C 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] = load capacitance operating voltage and f = average switching frequency ACTIVE CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 25˚ ...
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... Figure 23-2. Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) - Temp.=125°C Figure 23-3. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=25°C Atmel ATtiny24/44/84 [Preliminary] 188 ACTIVE CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 125˚C 1.2 1 0.8 0.6 0.4 0 0.1 0.2 ...
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... Figure 23-4. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=125°C Figure 23-5. Active Supply Current vs. V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ACTIVE CURRENT vs . FREQUENCY MHz - Temperature = 125˚ Frequency (MHz) ACTIVE CURRENT INTERNAL RC OSCILLATOR, 8 MHz 2 (Internal RC Oscillator, 8MHz) ...
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... Figure 23-6. Active Supply Current vs. V Figure 23-7. Active Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 190 ACTIVE CURRENT INTERNAL RC OSCILLATOR, 1MHz 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 ACTIVE CURRENT INTERNAL RC OSCILLATOR, 128 KHz 0.2 0.16 0.12 0.08 0. ...
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... Idle Supply Current Figure 23-8. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) Figure 23-9. Idle Supply Current vs. Frequency (1 - 20MHz) 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] IDLE CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 125˚C 0.012 0.01 0.008 0.006 0.004 ...
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... Figure 23-10. Idle Supply Current vs. V Figure 23-11. Idle Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 192 CC IDLE CURRENT INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 CC IDLE CURRENT INTERNAL RC OSCILLATOR, 1 MHz 0.35 0.3 0.25 0.2 0.15 ...
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... Figure 23-12. Idle Supply Current vs. V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] CC IDLE CURRENT INTERNAL RC OSCILLATOR, 128 KHz 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 2.5 3 3.5 (Internal RC Oscillator, 8MHz 4 (V) CC 125 ˚C 85 ˚C 25 ˚C -40 ˚C 5.5 193 ...
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... Table 23-1. PRR bit PRTIM1 PRTIM0 PRUSI PRADC 23.4 Power-down Supply Current Figure 23-13. Power-down Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 194 Additional Current Consumption for the different I/O modules (absolute values) Typical numbers 1MHz CC 6.6µA 8.7µA 5.5µA 22µ ...
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... Figure 23-14. Power-down Supply Current vs. V 23.5 Pin Pull-up Figure 23-15. I/O Pin Pull-up Resistor Current vs. input Voltage (V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] P OWER-DOWN CURRENT WATCHDOG TIMER ENABLED 2.5 3 3.5 I ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE 0.5 1 (Watchdog Timer Enabled) ...
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... Figure 23-16. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 23-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V Atmel ATtiny24/44/84 [Preliminary] 196 I ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE 160 140 120 100 0.5 1 1.5 2 RES ET P ULL-UP RES IS TOR CURRENT vs . RES VOLTAGE 60 -40 ˚ ...
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... Figure 23-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 23.6 Pin Driver Strength Figure 23-19. I/O Pin Output Voltage vs. Sink Current (V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] RES ET P ULL-UP RES IS TOR CURRENT vs . RES VOLTAGE 120 -40 ˚C 100 125 ˚ 0 ...
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... Figure 23-20. I/O pin Output Voltage vs. Sink Current (V Figure 23-21. I/O Pin Output Voltage vs. Source Current (V Atmel ATtiny24/44/84 [Preliminary] 198 I OUTP UT VOLTAGE INK CURRENT LOW POWER PINS - Vcc = 5.0V 0.7 0.6 0.5 0.4 0.3 0 OUTP UT VOLTAGE OURCE CURRENT LOW POWER PINS @ vcc = 3V 3 ...
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... Figure 23-22. I/O Pin output Voltage vs. Source Current (V 23.7 Pin Threshold and Hysteresis Figure 23-23. I/O Pin Input Threshold Voltage vs. V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] I OUTP UT VOLTAGE OURCE CURRENT LOW POWER PINS @ vcc = 5V 5.1 5 4.9 4.8 4.7 4.6 4.5 4 ...
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... Figure 23-24. I/O Pin Input threshold Voltage vs. V Figure 23-25. I/O Pin Input Hysteresis vs. V Atmel ATtiny24/44/84 [Preliminary] 200 I INP UT THRES HOLD VOLTAGE VIL, IO PIN READ AS '0' 2.5 2 1.5 1 0.5 0 2.5 3 3.5 I INP UT HYS TERES 0.5 0.45 0.4 0.35 0.3 0.25 ...