ATTINY44-15SSZ Atmel, ATTINY44-15SSZ Datasheet - Page 107
![IC MCU AVR 4K FLASH 15MHZ 14SOIC](/photos/7/39/73946/313-14-soic_sml.jpg)
ATTINY44-15SSZ
Manufacturer Part Number
ATTINY44-15SSZ
Description
IC MCU AVR 4K FLASH 15MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15SSZ.pdf
(225 pages)
Specifications of ATTINY44-15SSZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / Rohs Status
Details
Other names
Q3447517
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15SSZ
Manufacturer:
ATMEL
Quantity:
350
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14.9.4
7701E–AVR–02/11
Phase Correct PWM Mode
The phase correct pulse width modulation, or phase correct PWM, mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high-resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from bottom (0x0000) to top and then
from top to bottom.
In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare
match between TCNT1 and OCR1x while up-counting, and set on the compare match while
down-counting. In inverting output compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single-slope operation. However, due
to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8, 9, or 10 bits, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2 bits (ICR1 or OCR1A
set to 0x0003), and the maximum resolution is 16 bits (ICR1 or OCR1A set to max). The PWM
resolution in bits can be calculated by using the following equation:
In phase correct PWM mode, the counter is incremented until the counter value matches
either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in
ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then
reached the top, and changes the count direction. The TCNT1 value will be equal to top for
one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
ure 14-8 on page
used to define top. The TCNT1 value in the timing diagram is shown as a histogram for illus-
trating the dual-slope operation. The diagram includes non-inverted and inverted PWM
outputs. The small horizontal lines on the TCNT1 slopes represent compare matches between
OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs.
Figure 14-8. Phase Correct PWM Mode, Timing Diagram
TCNTn
OCnx
OCnx
Period
107. The figure shows phase correct PWM mode when OCR1A or ICR1 is
Atmel ATtiny24/44/84 [Preliminary]
1
R
PCPWM
2
=
log
---------------------------------- -
log
TOP
3
2
+
1
4
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Fig-
107
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