PIC18F25K20-I/ML Microchip Technology, PIC18F25K20-I/ML Datasheet - Page 14
![IC PIC MCU FLASH 16KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F25K20-I/ML
Manufacturer Part Number
PIC18F25K20-I/ML
Description
IC PIC MCU FLASH 16KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-EML.pdf
(430 pages)
Specifications of PIC18F25K20-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
64MHz
No. Of Timers
4
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F25K20-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2XK20/4XK20
FIGURE 3-2:
3.1.2
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.3 “ICSP Row Erase” and Section 3.2.1
“Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.3
“Data EEPROM Programming” and write ‘1’s to the
array.
DS41297F-page 14
PGC
PGD
4-bit Command
1
0
LOW-VOLTAGE ICSP BULK ERASE
2
0
3
1
4
1
P5
BULK ERASE TIMING DIAGRAM
1
1
Data Payload
2
1
16-bit
15 16
0
0
P5A
4-bit Command
1
0
Advance Information
2
0
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-bit
3.1.3
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data),
provided the block is not code or write-protected. Rows
are located at static boundaries beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 2.3 “Memory
Maps”).
The Row Erase duration is self-timed. After the WR bit
in EECON1 is set, two NOPs are issued. Erase starts
upon the 4th PGC of the second NOP. It ends when the
WR bit is cleared by hardware.
The code sequence to Row Erase a PIC18F2XK20/
4XK20 device is shown in Table 3-3. The flowchart
shown in Figure 3-3 depicts the logic necessary to com-
pletely erase a PIC18F2XK20/4XK20 device. The timing
diagram for Row Erase is identical to the data EEPROM
write timing shown in Figure 3-7.
15 16
Note:
0
0
P5A
4-bit Command
1
ICSP ROW ERASE
The TBLPTR register can point at any byte
within the row intended for erase.
0
2
0
3
0
4
0
© 2009 Microchip Technology Inc.
Erase Time
P11
P10
Data Payload
16-bit
1
n
2
n