PIC18F25K20-I/ML Microchip Technology, PIC18F25K20-I/ML Datasheet - Page 19
![IC PIC MCU FLASH 16KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F25K20-I/ML
Manufacturer Part Number
PIC18F25K20-I/ML
Description
IC PIC MCU FLASH 16KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-EML.pdf
(430 pages)
Specifications of PIC18F25K20-I/ML
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
64MHz
No. Of Timers
4
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F25K20-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.2.1
The previous programming example assumed that the
device has been Bulk Erased prior to programming
(see Section 3.1.1 “High-Voltage ICSP Bulk Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
TABLE 3-6:
© 2009 Microchip Technology Inc.
Step 1: Direct access to code memory.
Step 2: Read code memory into buffer (Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”).
Step 3: Set the Table Pointer for the block to be erased.
Step 4: Enable memory writes and setup an erase.
Step 5: Initiate erase.
Step 6: Poll WR bit. Repeat until bit is clear.
Step 7: Load write buffer. The correct bytes will be selected based on the Table Pointer.
To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes
(see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the
erase buffer.
Step 8: Disable writes.
Command
4-bit
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
0000
•
•
•
MODIFYING CODE MEMORY
MODIFYING CODE MEMORY
0E <Addr[21:16]>
0E <Addr[21:16]>
0E <Addr[8:15]>
0E <Addr[8:15]>
Data Payload
0E <Addr[7:0]>
0E <Addr[7:0]>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
9C A6
8E A6
6E F8
6E F7
6E F6
84 A6
88 A6
88 A6
82 A6
50 A6
6E F5
6E F8
6E F7
6E F6
94 A6
00 00
00 00
00 00
00 00
•
•
•
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
BSF
NOP
NOP
MOVF
MOVWF
NOP
Shift out data
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2 bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
BCF
Advance Information
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
EECON1, FREE
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, FREE
EECON1, WR
Erase starts on the 4th clock of this instruction
EECON1, W, 0
TABLAT
(1)
The appropriate number of bytes required for the erase
buffer must be read out of code memory (as described
in Section 4.2 “Verify Code Memory and ID Loca-
tions”) and buffered. Modifications can be made on
this buffer. Then, the block of code memory that was
read out must be erased and rewritten with the
modified data.
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
PIC18F2XK20/4XK20
Core Instruction
DS41297F-page 19