PIC18LF14K22-I/ML Microchip Technology, PIC18LF14K22-I/ML Datasheet - Page 205
![IC PIC MCU FLASH 512KX16 20-QFN](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC18LF14K22-I/ML
Manufacturer Part Number
PIC18LF14K22-I/ML
Description
IC PIC MCU FLASH 512KX16 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
4.PIC18LF14K22-IP.pdf
(382 pages)
Specifications of PIC18LF14K22-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF14K22-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18LF13K22-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF14K22-IP PDF datasheet #4
- Current page: 205 of 382
- Download datasheet (6Mb)
16.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
TABLE 16-1:
16.1.7
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 16-2 shows the two output formats.
FIGURE 16-2:
© 2009 Microchip Technology Inc.
Legend: Shaded cells are outside of recommended range.
Note 1:
ADC Clock Source
Note:
F
F
F
2:
3:
4:
(ADFM = 0)
(ADFM = 1)
F
F
F
OSC
OSC
OSC
OSC
OSC
OSC
F
ADC Clock Period (T
RC
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
RESULT FORMATTING
/16
/32
/64
/2
/4
/8
RC
ADC CLOCK PERIOD (T
source has a typical T
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
Unimplemented: Read as ‘0’
ADCS<2:0>
AD
000
100
001
101
010
110
x11
)
ADRESH
AD
10-bit A/D Result
time of 1.7 μs.
AD
41.67 ns
83.33 ns
) V
1-4 μs
167 ns
333 ns
667 ns
48 MHz
1.33 μs
Preliminary
S
. DEVICE OPERATING FREQUENCIES
MSB
(1,4)
AD
(2)
(2)
(2)
PIC18F1XK22/LF1XK22
(2)
(2)
time.
bit 0
bit 0
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 16.1.6
“Interrupts” for more information.
1-4 μs
RC
125 ns
250 ns
500 ns
Device Frequency (F
16 MHz
1.0 μs
2.0 μs
4.0 μs
clock source is only recommended if the
bit 7
bit 7
(1,4)
(2)
(2)
(2)
10-bit A/D Result
LSB
Unimplemented: Read as ‘0’
1-4 μs
16.0 μs
500 ns
8.0 μs
4 MHz
1.0 μs
2.0 μs
4.0 μs
ADRESL
OSC
(1,4)
(3)
(2)
(3)
)
DS41365C-page 205
1-4 μs
16.0 μs
32.0 μs
64.0 μs
8.0 μs
1 MHz
2.0 μs
4.0 μs
bit 0
LSB
bit 0
(1,4)
(3)
(3)
(3)
(3)
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