PIC18LF14K22-I/ML Microchip Technology, PIC18LF14K22-I/ML Datasheet - Page 220
![IC PIC MCU FLASH 512KX16 20-QFN](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC18LF14K22-I/ML
Manufacturer Part Number
PIC18LF14K22-I/ML
Description
IC PIC MCU FLASH 512KX16 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
4.PIC18LF14K22-IP.pdf
(382 pages)
Specifications of PIC18LF14K22-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF14K22-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18LF13K22-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF14K22-IP PDF datasheet #4
- Current page: 220 of 382
- Download datasheet (6Mb)
PIC18F1XK22/LF1XK22
17.2
Each
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
17-1 and 17-2, respectively) contain the control and
status bits for the following:
• Enable
• Input selection
• Reference selection
• Output selection
• Output polarity
• Speed selection
17.2.1
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
17.2.2
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
17.2.3
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting
Section 20.0
information on the Internal Voltage Reference module.
17.2.4
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
DS41365C-page 220
Note:
comparator
Comparator Control
COMPARATOR ENABLE
COMPARATOR INPUT SELECTION
To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
COMPARATOR REFERENCE
SELECTION
COMPARATOR OUTPUT
SELECTION
“V
input
OLTAGE
has
of
a
R
the
EFERENCES
separate
comparator.
” for
control
more
See
and
Preliminary
17.2.5
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 17-1 shows the output state versus input
conditions, including polarity control.
TABLE 17-1:
17.2.6
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
tion delay by clearing the CxSP bit to ‘0’.
17.3
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 25.0
“Electrical Specifications” for more details.
Input Condition
CxV
CxV
CxV
CxV
Note 1: The CxOE bit overrides the PORT data
IN
IN
IN
IN
- > CxV
- < CxV
- > CxV
- < CxV
2: The internal output of the comparator is
Comparator Response Time
COMPARATOR OUTPUT POLARITY
COMPARATOR SPEED SELECTION
latch. Setting the CxON has no impact on
the port override.
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
IN
IN
IN
IN
+
+
+
+
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
CxPOL
© 2009 Microchip Technology Inc.
0
0
1
1
CxOUT
0
1
1
0
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