ATTINY861V-10MU Atmel, ATTINY861V-10MU Datasheet - Page 130
ATTINY861V-10MU
Manufacturer Part Number
ATTINY861V-10MU
Description
IC MCU AVR 8K FLASH 10MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
32MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY861V-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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ATtiny261/461/861
Figure 13-4. Two-wire Mode Operation, Simplified Diagram
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
Figure 13-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram
SDA
SCL
1. The start condition is generated by the master by forcing the SDA low line while keep-
2. In addition, the start detector will hold the SCL line low after the master has forced a
ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the
USI Data Register, or by setting the corresponding bit in the PORTA register to zero.
Note that the Data Direction Register bit must be set to one for the output to be
enabled. The start detector logic of the slave device (see
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt
if necessary.
negative edge on this line (B). This allows the slave to wake up from sleep or complete
other tasks before setting up the USI Data Register to receive the address. This is done
by clearing the start condition flag and resetting the counter.
SLAVE
MASTER
A B
S
Bit7
Bit7
Bit6
Bit6
C
ADDRESS
1 - 7
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
R/W
(Figure
8
Bit2
Bit2
D
Bit1
Bit1
13-5), a bus transfer involves the following steps:
ACK
9
Bit0
Bit0
E
DATA
1 - 8
Two-wire Clock
Control Unit
ACK
9
PORTxn
Figure 13-6 on page
HOLD
SCL
DATA
1 - 8
SDA
SCL
SDA
SCL
ACK
9
VCC
2588E–AVR–08/10
131)
P
F
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