PIC16F72-I/SS Microchip Technology, PIC16F72-I/SS Datasheet - Page 53

• Manufacturer Part Number: PIC16F72-I/SS
• Description: IC PIC MCU FLASH 2KX14 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 8-bit
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.2
Master mode operation is supported in firmware using
interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a RESET or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle,
based on the START and STOP conditions. Control of
the I
bus is IDLE and both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So, when
transmitting data, a ‘1’ data bit must have the
TRISC<4> bit set (input) and a ‘0’ data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 = 1011), or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Master mode operation, see
AN554 - Software Implementation of I
TABLE 9-3:
© 2007 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
13h
93h
14h
94h
87h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Note 1: Maintain these bits clear in I
Address
2
C bus may be taken when the P bit is set, or the
Shaded cells are not used by SSP module in SPI mode.
MASTER MODE OPERATION
INTCON
PIR1
PIE1
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPADD Synchronous Serial Port (I
SSPCON
SSPSTAT SMP
TRISC
Name
REGISTERS ASSOCIATED WITH I
PORTC Data Direction Register
WCOL
Bit 7
GIE
—
—
(1)
SSPOV
CKE
ADIE
Bit 6
PEIE
ADIF
2
C mode.
(1)
2
C Bus Master.
TMR0IE
SSPEN
Bit 5
D/A
—
—
2
C mode) Address Register
INTE
Bit 4
CKP
—
—
P
2
SSPM3 SSPM2 SSPM1 SSPM0
SSPIE CCP1IE TMR2IE TMR1IE
SSPIF CCP1IF TMR2IF TMR1IF
C OPERATION
RBIE
Bit 3
S
9.3.3
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the START and STOP condi-
tions allows the determination of when the bus is free.
The STOP (P) and START (S) bits are cleared from a
RESET or when the SSP module is disabled. The
STOP (P) and START (S) bits will toggle, based on the
START and STOP conditions. Control of the I
may be taken when bit P (SSPSTAT<4>) is set, or the
bus is IDLE and both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the STOP condition occurs.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected out-
put level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the Slave device con-
tinues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data trans-
fer stage, the device will need to retransfer the data at
a later time.
For more information on Multi-Master mode operation,
see AN578 - Use of the SSP Module in the I
Multi-Master Environment.
TMR0IF
Bit 2
R/W
MULTI-MASTER MODE OPERATION
Bit 1
INTF
UA
RBIF
Bit 0
BF
PIC16F72
0000 000x
-0-- 0000 0000 0000
-0-- 0000 0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
POR, BOR
Value on
DS39597C-page 51
0000 000u
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111
Value on
RESETS
all other
2
C bus
2
C