PIC18F45K22-I/PT Microchip Technology, PIC18F45K22-I/PT Datasheet - Page 354

• Manufacturer Part Number: PIC18F45K22-I/PT
• Description: MCU 8BIT 32KB FLASH 5.5V 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K22-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Processor Series: PIC18F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
REGISTER 24-4:
DS41412D-page 354
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
MCLRE
R/P-1
2:
PIC18(L)F2XK22 devices only.
PIC18(L)F4XK22 devices only.
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
Unimplemented: Read as ‘0’
P2BMX: P2B Input MUX bit
1 = P2B is on RB5
0 = P2B is on RC0
T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5
HFOFST: HFINTOSC Fast Start-up bit
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize
0 = The system clock is held off until the HFINTOSC is stable
CCP3MX: CCP3 MUX bit
1 = CCP3 input/output is multiplexed with RB5
0 = CCP3 input/output is multiplexed with RC6
PBADEN: PORTB A/D Enable bit
1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset
0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset
CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
CCP3 input/output is multiplexed with RE0
P2B is on RD2
U-0
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH
P = Programmable bit
P2BMX
R/P-1
(1)
(2)
T3CMX
R/P-1
Preliminary
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
HFOFST
(2)
(1)
R/P-1
CCP3MX
R/P-1
 2010 Microchip Technology Inc.
PBADEN
R/P-1
CCP2MX
R/P-1
bit 0