PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet
PIC18F2221-I/SS
Specifications of PIC18F2221-I/SS
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PIC18F2221-I/SS Summary of contents
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... Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2007 Microchip Technology Inc. PIC18F4321 Family Data Sheet 28/40/44-Pin Preliminary DS39689E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart - Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F2221 4K 2048 PIC18F2321 8K 4096 PIC18F4221 4K 2048 PIC18F4321 8K 4096 © 2007 Microchip Technology Inc. ...
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... RB3 is the alternate pin for CCP2 multiplexing. DS39689E-page /RE3 REF REF ( / REF 2 20 REF PIC18F2221 4 18 PIC18F2321 Preliminary RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA (1) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT © 2007 Microchip Technology Inc. ...
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... RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note 1: RB3 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY /RE3 REF 37 + REF ...
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... Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. DS39689E-page 4 NC/ICRST 33 1 RC0/T1OSO/T13CKI 32 2 OSC2/CLKO/RA6 OSC1/CLKI/RA7 4 PIC18F4221 PIC18F4321 RE2/CS/AN7 27 7 RE1/WR/AN6 26 8 RE0/RD/AN5 9 25 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT 11 Preliminary (2) (2) /ICV PP © 2007 Microchip Technology Inc. ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 379 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 379 Index ................................................................................................................................................................................................. 381 The Microchip Web Site ..................................................................................................................................................................... 391 Customer Change Notification Service .............................................................................................................................................. 391 Customer Support .............................................................................................................................................................................. 391 Reader Response .............................................................................................................................................................................. 392 PIC18F2221/2321/4221/4321 Product Identification System ............................................................................................................ 393 © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39689E-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F2221 • PIC18LF2221 • PIC18F2321 • PIC18LF2321 • PIC18F4221 • PIC18LF4221 • PIC18F4321 • PIC18LF4321 This family offers the advantages of all PIC18 micro- controllers – namely, high computational performance at an economical price – ...
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... Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory PIC18F2221/4221 PIC18F2321/4321). 2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). 3. I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). ...
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... Resets (and Delays) RESET Instruction, Stack Underflow MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Packages © 2007 Microchip Technology Inc. PIC18F4321 FAMILY PIC18F2221 PIC18F2321 DC – 40 MHz DC – 40 MHz 4096 8192 2048 4096 512 512 256 256 19 ...
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... PIC18F4321 FAMILY FIGURE 1-1: PIC18F2221/2321 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (4 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine ...
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... RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Data Bus<8> Data Latch ...
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... PIC18F4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, Pin Name SOIC, QFN SSOP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/C1OUT 6 3 RA4 T0CKI C1OUT RA5/AN4/SS/HLVDIN/ ...
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... PIC18F4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (2) CCP2 RB4/KBI0/AN11 25 22 RB4 ...
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... TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RC0/T1OSO/T13CKI 11 8 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 12 9 RC1 T1OSI (1) CCP2 RC2/CCP1 13 10 RC2 CCP1 RC3/SCK/SCL 14 11 RC3 SCK SCL RC4/SDI/SDA 15 12 RC4 SDI SDA RC5/SDO 16 13 ...
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... In RC, EC and INTIO modes, OSC2 pin outputs CLKO which has one-fourth the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input O = Output Preliminary Description P = Power © 2007 Microchip Technology Inc. ...
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... Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input O = Output Preliminary Description P = Power © 2007 Microchip Technology Inc. ...
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... Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input O = Output Preliminary Description P = Power © 2007 Microchip Technology Inc. ...
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... Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 22 Preliminary © 2007 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2007 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT 20 pF ≤ C ≤ 300 pF EXT © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Locked Loop (PLL) in Internal Oscillator modes (see Figure 2-10). FIGURE 2-10: /4, OSC (OSCTUNE<6>) INTOSC CLKO OSC2 RA6 Preliminary by writing to TUN4:TUN0 in the OSCTUNE register INTOSC AND PLL BLOCK DIAGRAM MHz PLLEN Phase F IN Comparator F OUT Loop Filter ÷4 VCO SYSCLK © 2007 Microchip Technology Inc. ...
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... Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • 10000 = Minimum frequency Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift affect the controller operation in a variety of ways ...
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... To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary © 2007 Microchip Technology Inc. ...
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... WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F4321 family of devices are shown in Figure 2-11. See Section 23.0 “Special Features of the CPU” for Configuration register details. PIC18F2221/2321/4221/4321 HSPLL, INTOSC/PLL 4 x PLL OSCTUNE<6> OSCCON<6:4> ...
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... This formula assumes register that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. Preliminary © 2007 Microchip Technology Inc. ...
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... Modifying the SCSI:SCSO bits will cause an immediate clock source switch. 5: Modifying the IRCF3:IRCF0 bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY (1) R/W-0 R/W-0 R ...
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... EC INTIO modes are used as the primary clock source. are listed in OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level Preliminary (parameter 38, CSD OSC2 Pin © 2007 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary © 2007 Microchip Technology Inc. ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) T (1) OST T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set ; (approx). These intervals are not shown to scale. PLL . OSC Preliminary © 2007 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscil- lator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2007 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... LP, XT OST HSPLL T OST EC CSD (2) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Preliminary Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (3) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS © 2007 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1 ...
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... POR was set to ‘1’ by software immediately after Power-on Reset). DS39689E-page 42 (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY FIGURE 4-2: V ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Preliminary © 2007 Microchip Technology Inc. ...
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... Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in HSPLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39689E-page 46 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2007 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F4321 FAMILY , V RISE > PWRT T OST T PWRT T OST ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter POR BOR STKFUL 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ( Preliminary © 2007 Microchip Technology Inc. STKPTR Register STKUNF ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... NOP instruction). The PIC18F2221 and PIC18F4221 each have 4 Kbytes of Flash memory and can store up to 2048 single-word instructions. The PIC18F2321 and PIC18F4321 each have 8 Kbytes of Flash memory and can store up to 4096 single-word instructions ...
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... Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary RCALL or interrupt, the can return these values to Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary © 2007 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 7 Data Memory ...
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... F90h — (2) F8Fh — (2) F8Eh — (3) F8Dh LATE (3) F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA (2) F88h — (1) (2) F87h — (2) F86h — (2) F85h — (3) F84h PORTE (3) F83h PORTD F82h PORTC F81h PORTB F80h PORTA © 2007 Microchip Technology Inc. ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) (6) (6) STKPTR STKFUL STKUNF — PCLATU — — Holding Register for PC<21:16> PCLATH Holding Register for PC<15:8> ...
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... PIC18F4321 FAMILY TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — — (1) RCON ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte RCREG EUSART Receive Register TXREG EUSART Transmit Register TXSTA CSRC TX9 TXEN RCSTA ...
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... The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-x R/W-x R/W bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2007 Microchip Technology Inc. ...
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... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory Preliminary © 2007 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... Bank 0 addresses below 5Fh can still be addressed F80h by using the BSR. FFFh © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘ ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 72 Preliminary © 2007 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Preliminary Table Latch (8-bit) TABLAT © 2007 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-x R/W-0 — ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:3> TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE TBLPTR<2:0> © 2007 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F4321 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2007 Microchip Technology Inc. ...
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... CFGS bit to access program memory; • set WREN to enable byte writes. 8. Disable interrupts. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
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... FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full Preliminary © 2007 Microchip Technology Inc. ...
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... PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 82 Preliminary © 2007 Microchip Technology Inc. ...
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... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
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... Does not initiate an EEPROM read Legend Readable bit -n = Value at POR DS39689E-page 84 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 87
... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 88
... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — FREE WRERR WREN — ...
Page 90
... PIC18F4321 FAMILY NOTES: DS39689E-page 88 Preliminary © 2007 Microchip Technology Inc. ...
Page 91
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F4321 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 92
... MOVF ARG1L, W SUBWF RES2 MOVF ARG1H, W SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H, 7 BRA CONT_CODE MOVF ARG2L, W SUBWF RES2 MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : Preliminary © 2007 Microchip Technology Inc ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ...
Page 93
... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...
Page 94
... INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2007 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 95
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 96
... This feature allows for software polling. DS39689E-page 94 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 97
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 ...
Page 98
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 99
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-0 R/W-0 — EEIF BCLIF ...
Page 100
... R = Readable bit -n = Value at POR DS39689E-page 98 R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown ...
Page 101
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-0 R/W-0 — EEIE BCLIE HLVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 102
... R = Readable bit -n = Value at POR DS39689E-page 100 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown ...
Page 103
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-1 R/W-1 R/W-1 — EEIP BCLIP HLVDIP W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 104
... Section 4.1 “RCON Register”. (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 105
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 106
... PIC18F4321 FAMILY NOTES: DS39689E-page 104 Preliminary © 2007 Microchip Technology Inc. ...
Page 107
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...
Page 108
... System cycle clock output (F modes. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. I ANA Main oscillator input connection. I ANA Main clock input connection. Preliminary Description /4) in RC, INTIO1 and EC Oscillator OSC © 2007 Microchip Technology Inc. ...
Page 109
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 ...
Page 110
... PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the Configuration bit, CCP2MX, as the alternate peripheral pin for the CCP2 module (CCP2MX = 0). bit, Preliminary © 2007 Microchip Technology Inc. ...
Page 111
... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY I/O I/O Type ...
Page 112
... Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 49 — RBIP 49 INT2IF INT1IF 49 PCFG1 PCFG0 51 © 2007 Microchip Technology Inc. ...
Page 113
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note Power-on Reset, these pins are configured as digital inputs ...
Page 114
... I ST PORTC<7> data input Asynchronous serial receive data input (EUSART module). O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Preliminary Description © 2007 Microchip Technology Inc. ...
Page 115
... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary ...
Page 116
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2007 Microchip Technology Inc. ...
Page 117
... P1D 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY I/O I/O Type O DIG LATD< ...
Page 118
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39689E-page 116 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 52 CCP1M1 CCP1M0 51 © 2007 Microchip Technology Inc. ...
Page 119
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 120
... Value at POR DS39689E-page 118 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY I/O I/O ...
Page 122
... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V Preliminary PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2007 Microchip Technology Inc. ...
Page 123
... ADIE (1) IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 ...
Page 124
... PIC18F4321 FAMILY NOTES: DS39689E-page 122 Preliminary © 2007 Microchip Technology Inc. ...
Page 125
... Prescale value Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 126
... Sync with Internal TMR0L Clocks Delay) OSC 3 Preliminary ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 127
... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 128
... PIC18F4321 FAMILY NOTES: DS39689E-page 126 Preliminary © 2007 Microchip Technology Inc. ...
Page 129
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 130
... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Peripheral Clock Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Peripheral Clock Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 131
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 132
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary © 2007 Microchip Technology Inc. ...
Page 133
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 134
... PIC18F4321 FAMILY NOTES: DS39689E-page 132 Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 136
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP © 2007 Microchip Technology Inc. ...
Page 137
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 138
... Clear TMR3 TMR3L 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 139
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 140
... PIC18F4321 FAMILY NOTES: DS39689E-page 138 Preliminary © 2007 Microchip Technology Inc. ...
Page 141
... CCPx match (CCPxIF bit is set) 11xx = PWM mode Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. Note: Throughout this section and Section 16.0 “ ...
Page 142
... Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropri- ate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction Preliminary © 2007 Microchip Technology Inc. ...
Page 143
... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 144
... Set CCP1IF Compare Output Match Logic 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Logic Match 4 CCP2CON<3:0> Preliminary Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2007 Microchip Technology Inc. ...
Page 145
... The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 ...
Page 146
... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Preliminary • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2007 Microchip Technology Inc. ...
Page 147
... The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY EQUATION 15-3: PWM Resolution (max) Note: ...
Page 148
... PSSAC1 PSSAC0 PSSBD1 (2) (2) (2) PDC5 PDC4 PDC3 PDC2 Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 51 (2) (2) PSSBD0 51 (2) (2) (2) PDC1 PDC0 51 © 2007 Microchip Technology Inc. ...
Page 149
... ECCP module are the same as described for the standard CCP module. The control register for the Enhanced CCP module is shown in Register 16-1. It differs from the CCPxCON registers in PIC18F2221/2321 devices in that the two Most Significant bits are implemented to control PWM functionality. R/W-0 ...
Page 150
... PWM. and Timer RC2 RD5 All 40/44-pin devices: CCP1 RD5/PSP5 P1A P1B P1A P1B Preliminary and Section 15.3 “Compare the processes described in “Setup for PWM RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2007 Microchip Technology Inc. ...
Page 151
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 152
... The general relationship of the outputs in all configurations is summarized in Figure 16-2. 9.77 kHz 39.06 kHz FFh FFh Preliminary OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2007 Microchip Technology Inc. ...
Page 153
... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay ...
Page 154
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...
Page 155
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 156
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD © 2007 Microchip Technology Inc. ...
Page 157
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F4321 FAMILY (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...
Page 158
... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 (1) (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Unimplemented on 28-pin devices; bits read as ‘0’. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 ( Writable bit U = Unimplemented bit, read as ‘ ...
Page 160
... PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle Preliminary © 2007 Microchip Technology Inc. ECCPASE Cleared by Firmware ...
Page 161
... Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 162
... Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP 52 TMR3IF CCP2IF 52 TMR3IE CCP2IE 52 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 51 (2) (2) PSSBD1 PSSBD0 51 (2) (2) (2) PDC2 PDC1 PDC0 51 © 2007 Microchip Technology Inc. ...
Page 163
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four SPI modes are supported ...
Page 164
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 165
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented C™ mode only. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ...
Page 166
... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. Preliminary © 2007 Microchip Technology Inc. ...
Page 167
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers ...
Page 168
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 169
... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F4321 FAMILY SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39689E-page 168 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary ) 0 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
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... These bits are unimplemented on 28-pin devices and read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg) Preliminary 2 C operation mode operation. The 2 C Slave mode. When the © 2007 Microchip Technology Inc. ...
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... SSPBUF is empty In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2 C™ MODE) R-0 R-0 R-0 ...
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... CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for Bit is unknown © 2007 Microchip Technology Inc. ...
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... In Slave mode (7-bit Address mode Address masking of ADD1 enabled 0 = Address masking of ADD1 disabled In Slave mode (10-bit Address mode Address masking of ADD1 and ADD0 enabled 0 = Address masking of ADD1 and ADD0 disabled © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2 C™ MODE) R/W-0 R/W-0 ...
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... U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 (1) (1) (1) / RSEN / SEN ADMSK1 bit 0 C module is active, these bits x = Bit is unknown R/W-0 R/W-0 ADD1 ADD0 bit Master x = Bit is unknown © 2007 Microchip Technology Inc. ...
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... The high and low times of the specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register ...
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... They only affect the lower address bits. Note 1: ADMSK<1> Significant bits of the address. 2: The two Most Significant bits of the address are not affected by address masking. Preliminary bits, ADMSK<5:2>, mask the masks the two Least © 2007 Microchip Technology Inc. ...
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... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F4321 FAMILY 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39689E-page 178 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 179 ...
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... PIC18F4321 FAMILY 2 FIGURE 17-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39689E-page 180 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK = 01001 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 181 ...
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... PIC18F4321 FAMILY 2 FIGURE 17-12: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39689E-page 182 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 183 ...
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... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 17-13). Preliminary © 2007 Microchip Technology Inc. ...
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... SDA DX SCL CKP WR SSPCON © 2007 Microchip Technology Inc. PIC18F4321 FAMILY already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-14) ...
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... PIC18F4321 FAMILY 2 FIGURE 17-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39689E-page 186 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-16: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 187 ...
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... Acknowledge (Figure 17-17). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Preliminary Receiving Data ACK ‘0’ ‘1’ © 2007 Microchip Technology Inc. ...
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... Generate a Stop condition on SDA and SCL. FIGURE 17-18: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
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... SSPCON2 register. 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. Preliminary © 2007 Microchip Technology Inc. ...
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... The I C™ interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
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... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count Preliminary 03h 02h © 2007 Microchip Technology Inc. ...
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... FIGURE 17-21: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG 1st bit Write to SSPBUF occurs here T BRG Sr = Repeated Start Preliminary T BRG © 2007 Microchip Technology Inc. ...
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... CY updated. This may result in a corrupted transfer. The user should verify that the WCOL flag is clear after each write to SSPBUF to ensure the transfer is correct. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC18F4321 FAMILY 2 FIGURE 17-23: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39689E-page 196 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-24: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 197 ...
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... PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Preliminary later, the PEN bit is BRG Cleared in software BRG © 2007 Microchip Technology Inc. ...