ATMEGA16-16AU SL383 Atmel, ATMEGA16-16AU SL383 Datasheet - Page 43
![IC MCU 8BIT 16KB FLASH 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16-16AU SL383
Manufacturer Part Number
ATMEGA16-16AU SL383
Description
IC MCU 8BIT 16KB FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16L-8MI.pdf
(357 pages)
Specifications of ATMEGA16-16AU SL383
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 43 of 357
- Download datasheet (8Mb)
Watchdog Timer
Control Register –
WDTCR
2466T–AVR–07/10
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega16 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 17. Watchdog Timer Prescale Select
Bit
Read/Write
Initial Value
WDP2
0
0
0
0
1
1
1
1
ten to WDE even though it is set to one before the disable operation starts.
WDP1
0
0
1
1
0
0
1
1
Table
R
7
–
0
WDP0
17.
0
1
0
1
0
1
0
1
R
6
–
0
1,024K (1,048,576)
2,048K (2,097,152)
Oscillator Cycles
Number of WDT
128K (131,072)
256K (262,144)
512K (524,288)
16K (16,384)
32K (32,768)
64K (65,536)
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
Typical Time-out
at V
WDP2
17.1 ms
34.3 ms
68.5 ms
R/W
0.14 s
0.27 s
0.55 s
CC
1.1 s
2.2 s
2
0
= 3.0V
WDP1
R/W
1
0
Typical Time-out
ATmega16(L)
WDP0
at V
R/W
0
0
16.3 ms
32.5 ms
65 ms
0.13 s
0.26 s
0.52 s
CC
1.0 s
2.1 s
= 5.0V
WDTCR
43
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