AT90PWM316-16SU Atmel, AT90PWM316-16SU Datasheet
AT90PWM316-16SU
Specifications of AT90PWM316-16SU
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AT90PWM316-16SU Summary of contents
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... Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) 8-bit Microcontroller with 16K Bytes In-System Programmable Flash AT90PWM216 AT90PWM316 7710E–AVR–08/10 ...
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... SO24 SO32, AT90PWM316 QFN32 1. History Product AT90PWM216 AT90PWM316 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized. AT90PWM216/316 2 ADC ADC ...
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Pin Configurations Figure 3-1. Figure 3-2. 7710E–AVR–08/10 SOIC 24-pin Package SOIC 32-pin Package AT90PWM216/316 3 ...
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Figure 3-3. (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 3.1 Pin Descriptions : Table 3-1. Pin out description S024 Pin SO32 Pin QFN32 Pin Number Number Number AT90PWM216/316 4 QFN32 (7*7 mm) Package. AT9 0PWM316 1 2 ...
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Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number ...
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Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number ...
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Block Diagram Figure 4-1. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in ...
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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C is not available on 24 pins package. Port C also serves the functions of special features of the AT90PWM316 as listed on AT90PWM216/316 8 AT90PWM216 device is available in SOIC 24-pin Package and does not have the D2A (DAC Out- put) brought out to I/0 pins ...
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Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...
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AVR CPU Core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 5.5 General Purpose Register File The Register File is optimized for the ...
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Figure 5-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 Stack Pointer The Stack is mainly used for storing ...
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Figure 5-4 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ...
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BOOTRST Fuse, see gramming” on page 5.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 5.8.2 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is ...
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Memories This section describes the different memories in the AT90PWM216/316. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM216/316 features an EEPROM Memory for data storage. All three ...
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The AT90PWM216/316 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, ...
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Figure 6-3. 6.3 EEPROM Data Memory The AT90PWM216/316 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at ...
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The EEPROM Address Registers – EEARH and EEARL Bit Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address ...
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Table 6-1. EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. ...
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When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob- ally) so that no interrupts will occur during execution of these functions. ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. TABLE 4. Assembly Code Example EEPROM_read: C Code ...
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I/O Memory The I/O space definition of the AT90PWM216/316 is shown in All AT90PWM216/316 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...
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General Purpose I/O Register 3– GPIOR3 Bit Read/Write Initial Value 7710E–AVR–08/ GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 R/W R/W R/W R AT90PWM216/316 GPIOR3 R/W R/W ...
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System Clock 7.1 Clock Systems and their Distribution Figure 7-1 need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 7.1.4 PLL Clock – clk PLL The PLL clock allows the PSC modules ...
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Watchdog Oscillator is voltage dependent as shown in Frequency vs. VCC” on page Table 7-2. Typ Time-out (V 7.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The ...
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The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3. CKSEL3..1 100 101 110 111 Notes: The CKSEL0 Fuse together with ...
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Table 7-4. CKSEL0 Notes: 7.5 Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately ...
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Table 7-5. Notes: When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7-6 on page Table 7-6. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 7.5.1 Oscillator Calibration Register ...
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PLL To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of PLL must be configurable by software. With ...
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Figure 7-3. XTAL1 XTAL2 7.6.2 PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and always read as zero. • Bit ...
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Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator. 7.8 External ...
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If the System Clock Prescaler is used the divided system clock that is output (CKOUT Fuse programmed). 7.10 System Clock Prescaler The AT90PWM216/316 system clock can be divided by setting the Clock Prescale Register ...
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The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This ...
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Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Table 8-2. Sleep Mode Idle ADC Noise Reduction Power- down Standby Notes: 8.5 Power Reduction Register The Power Reduction Register, ...
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Bit 6 - PRPSC1: Power Reduction PSC1 Writing a logic one to this bit reduces the consumption of the PSC1 by stopping the clock to this module. When waking up the PSC1 again, the PSC1 should be re initialized ...
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Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, ...
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System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 9-1. Table 9-1. Symbol V POT V RST t RST Notes: 9.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger ...
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Figure 9-2. Figure 9-3. 9.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the ...
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Brown-out Detection AT90PWM216/316 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The ...
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Figure 9-5. 9.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 50 ...
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Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on ...
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Watchdog Timer AT90PWM216/316 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms ...
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In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
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Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt. WDIF is cleared by hardware when executing the corresponding ...
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Table 9-6. WDP3 AT90PWM216/316 54 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles 0 ...
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Interrupts ...
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Table 10-1. Vector No Notes: Table 10-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are ...
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Self-Programming” on page 266 tables, a special write procedure must be followed to change the IVSEL bit: a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing ...
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I/O-Ports 11.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 11-2. General Digital I/O Note: 11.2.1 Configuring the Pin Each port pin consists ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 11-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock ...
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TABLE 2. Assembly Code Example ... ; Define pull-ups and set ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...
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Table 11-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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ADC7/ICP1B/PSCOUT11 – Bit 6 ADC7, Analog to Digital Converter, input channel 7 ICP1B, Input Capture Pin: The PB6 pin can act as an Input Capture Pin for Timer/Counter1. PSCOUT11: Output 1 of PSC 1. • ADC6/INT2 – Bit 5 ...
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Table 11-4 shown in Table 11-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 11-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 7710E–AVR–08/10 and Table 11-5 relates the alternate functions ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 11-6. The alternate pin configuration is as follows: • D2A – Bit 7 D2A, Digital to Analog output • ADC10/ACMP1 – Bit 6 ...
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T0/PSCOUT22 – Bit 2 T0, Timer/Counter0 counter source. PSCOUT22: Output 2 of PSC 2. • PSCIN1/OC1B, Bit 1 PCSIN1, PSC 1 Digital Input. OC1B, Output Compare Match B output: This pin can serve as an external output for the ...
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Table 11-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO AT90PWM216/316 72 Overriding Signals for Alternate Functions in PC3..PC0 PC3/T1/ PC2/T0/ PSCOUT23 PSCOUT22 PSCen23 PSCen22 1 1 PSCen23 PSCen22 PSCout23 PSCout22 T1 ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 11-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ACMP0 – Bit 7 ...
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ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Ana- log Comparator. • ADC1/RXD/ICP1/SCK_A – Bit 4 ADC1, ...
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CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTD1 and DDD1 settings. It will also be output during ...
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Table 11-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 11.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 11-12. Port ...
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XTAL1/OC0B – Bit 1 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. OC0B, Output ...
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Register Description for I/O-Ports 11.4.1 Port B Data Register – PORTB Bit Read/Write Initial Value 11.4.2 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 11.4.3 Port B Input Pins Address – PINB Bit Read/Write Initial Value ...
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Port D Input Pins Address – PIND Bit Read/Write Initial Value 11.4.10 Port E Data Register – PORTE Bit Read/Write Initial Value 11.4.11 Port E Data Direction Register – DDRE Bit Read/Write Initial Value 11.4.12 Port E Input Pins ...
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External Interrupts The External Interrupts are triggered by the INT3:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. ...
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Table 12-1. ISCn1 Note: 12.0.2 External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bits 3..0 – INT3 – INT0: External Interrupt Request Enable When an INT3 – INT0 bit is ...
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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.0.1 Internal Clock Source The Timer/Counter can be clocked directly ...
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum ...
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Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PB6). The selection is made thanks to ICPSEL1 bit as described in Table 13-1. ICPSEL1 0 1 • Bit 0 – PSRSYNC: Prescaler Reset When this bit is ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...
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TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in AT90PWM216/316 86 Table 14-1 are also used extensively throughout the document. 7710E–AVR–08/10 ...
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Table 14-1. BOTTOM MAX TOP 14.1.2 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All ...
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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = ...
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Figure 14-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in ...
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PWM refer to A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be ...
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Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 14-6. Fast PWM Mode, ...
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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...
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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see visible on the port pin if the data direction for the port pin is ...
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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 14-10 mode and PWM mode, where OCR0A is TOP. Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk I/O TCNTn ...
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Timer/Counter Register Description 14.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 14-4 rect PWM mode. Table 14-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...
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Table 14-7 rect PWM mode. Table 14-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bits 1:0 – WGM01:0: ...
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Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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Table 14-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of ...
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Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt ...
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Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.1.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in ...
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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of ...
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TABLE 2. Assembly Code Examples ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples unsigned int i; ... /* Set TCNTn to ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. TABLE 2. Assembly Code Example TIM16_ReadTCNTn: C Code ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. TABLE 2. Assembly Code Example TIM16_WriteTCNTn: ; Save ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 15.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written ...
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Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next “timer clock cycle”. ...
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The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis- abled the CPU will access the OCRnx ...
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PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin system reset occur, the OCnx Register is reset ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode ...
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Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max- imum resolution is 16-bit ...
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When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next ...
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OCRnA set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...
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TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...
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OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...
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Figure 15-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
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Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.10 16-bit Timer/Counter Register Description 15.10.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit ...
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Table 15-3 PWM mode. Table 15-3. COMnA1/COMnB1 Note: Table 15-4 correct or the phase and frequency correct, PWM mode. Table 15-4. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB ...
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Table 15-5. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
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When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 15.10.4 Timer/Counter1 – TCNT1H and TCNT1L ...
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The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. ...
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Timer/Counter1 Interrupt Flag Register – TIFR1 Bit Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM216/316, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input ...
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Power Stage Controller – (PSC0, PSC1 & PSC2) The Power Stage Controller is a high performance waveform controller. 16.1 Features • PWM waveform generation function (2 complementary programmable outputs) • Dead time control • Standard mode ...
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PSC Description Figure 16-1. Power Stage Controller Block Diagram Note: The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to count up and count down from ...
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PSC2 Distinctive Feature Figure 16-2. PSC2 versus PSC1&PSC0 Block Diagram Note: PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23. Thanks to a first selector PSCOUT22 can duplicate PSCOUT20 or PSCOUT21. Thanks to a second selector PSCOUT23 can duplicate PSCOUT20 ...
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Signal Description Figure 16-3. PSC External Block View Note: 16.4.1 Input Description Table 16-1. Name OCRnRB[1 1:0] OCRnSB[1 1:0] OCRnRA[1 1:0] OCRnSA[1 1:0] AT90PWM216/316 134 CLK PLL CLK I/O SYnIn StopOut 12 OCRnRB[11:0] 12 OCRnSB[11:0] 12 OCRnRA[11:0] 12 OCRnSA[11:0] ...
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Name OCRnRB[1 5:12] CLK I/O CLK PLL SYnIn StopIn Note: Table 16-2. Name PSCINn from A C 16.4.2 Output Description Table 16-3. Name PSCOUTn0 PSCOUTn1 PSCOUTn2 (PSC2 only) PSCOUTn3( PSC2 only) Table 16-4. Name SYnOut PICRn [11:0] IRQPSCn PSCnASY StopOut ...
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Functional Description 16.5.1 Waveform Cycles The waveform generated by PSC can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform is sub-cycle ...
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Running Mode Description Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1, OT1) and by the running mode. Four modes are possible : – Four Ramp mode – Two Ramp mode – One Ramp ...
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Figure 16-7. PSCn0 & PSCn1 Basic Waveforms in Two Ramp mode PSC Counter PSCOUTn0 PSCOUTn1 PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = (OCRnRAH/L - OCRnSAH/L) ...
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Figure 16-8. PSCn0 & PSCn1 Basic Waveforms in One Ramp mode PSC Counter PSCOUTn0 PSCOUTn1 On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time ...
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Figure 16-9. PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode On-Time OCRnSAH/L * 1/Fclkpsc On-Time (OCRnRBH/L - OCRnSBH 1/Fclkpsc Dead-Time = (OCRnSBH/L - OCRnSAH/L) * 1/Fclkpsc PSC Cycle ...
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Fifty Percent Waveform Configuration When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRn- SBH/L and OCRnRBH/L registers in ...
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The resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is given by OCRnRB[15:12]. The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) ...
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Frequency distribution The frequency modulation is done by switching two frequencies consecutive cycle frame. These two frequencies are f frequency and f in the frame is (d-16) and the number of f uted in the frame ...
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Modes of Operation 16.7.2.1 Normal Mode The simplest mode of operation is the normal mode. See The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both ...
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PSC Inputs Each part PSC has its own system to take into account one PSC input. According to PSC n Input A/B Control Register (see description has a Retrigger or Fault input. This system A ...
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Figure 16-15. PSCOUTn0 retriggered by PSCn Input A (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Note: Figure 16-16. PSCOUTn0 retriggered by PSCn Input A (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input A (high level) ...
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Figure 16-17. PSCOUTn1 retriggered by PSCn Input B (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Note: Figure 16-18. PSCOUTn1 retriggered by PSCn Input B (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input B (high level) ...
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Figure 16-19. Burst Generation PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 16.8.4 PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. 16.8.4.1 Filter Enable If the “Filter Enable” bit ...
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If PELEVnx bit set, the significant edge of PSCn Input rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - 4-ramp mode, PSCn Input A is ...
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PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 16-20. PSCn behaviour versus PSCn Input A in Fault Mode 1 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is ...
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PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait Figure 16-22. PSCn behaviour versus PSCn Input A in Fault Mode 2 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is take ...
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PSC Input Mode 3: Stop signal, Execute Opposite while Fault active Figure 16-24. PSCn behaviour versus PSCn Input A in Mode 3 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken ...
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Figure 16-26. PSC behaviour versus PSCn Input A or Input B in Mode 4 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 16-27. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4 ...
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PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. Figure 16-29. PSC behaviour versus PSCn Input A in Fault Mode 6 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Used in Fault mode ...
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Figure 16-31. PSC behaviour versus PSCn Input A in Mode 8 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurence of significative edge of retriggering input. Figure 16-32. PSC behaviour versus PSCn Input B ...
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Figure 16-33. PSC behaviour versus PSCn Input A in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurence of significative edge of retriggering input. Only the output is disactivated when significative ...
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Figure 16-35. PSC behaviour versus PSCn Input A in Mode 14 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurence of significative edge of retriggering input. Figure 16-36. PSC behaviour versus PSCn ...
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Table 16-7. Input Mode Number : 16.18.2 Event Capture The PSC can capture the value of time (PSC counter) when a retrigger event or fault event occurs on PSC inputs. ...
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PSC2 Outputs 16.19.1 Output Matrix PSC2 has an output matrix which allow in 4 ramp mode to program a value of PSCOUT20 and PSCOUT21 binary value for each ramp. Table 16-8. PSCOUT20 PSCOUT21 PSCOUT2m takes the value given in ...
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This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs. In center aligned mode, OCRnRAH/L is not used can be used to specified the synchroniza- tion of the ADC. It this case, ...
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PRUNn and PARUNn bits are located in PCTLn register. on page 166. See “PSC 1 Control Register – PCTL1” on page 167. See “PSC 2 Control Register – PCTL2” on page 168. Note : Do not set the PARUNn bits ...
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Table 16-9. PCLKSELn 16.24 Interrupts ...
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PSC 0 Synchro and Output Configuration – PSOC0 Bit Read/Write Initial Value 16.25.2 PSC 1 Synchro and Output Configuration – PSOC1 Bit Read/Write Initial Value 16.25.3 PSC 2 Synchro and Output Configuration – PSOC2 Bit Read/Write Initial Value • ...
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Bit 3 – POEN2D : PSCOUT23 Output Enable (PSC2 only) When this bit is clear, second I/O pin affected to PSCOUT23 acts as a standard port. When this bit is set, second I/O pin affected to PSCOUT23 is connected ...
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The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value. A match can be used to generate an Output Compare interrupt generate a waveform output on ...
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Table 16-13. PSC n Mode Selection PMODEn1 • Bit 2 – POPn: PSC n Output Polarity If this bit is cleared, the PSC outputs are active Low. If this bit is set, the PSC outputs are ...
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Bit 4 – PAOC0B : PSC 0 Asynchronous Output Control B When this bit is set, Fault input selected to block B can act directly to PSCOUT01 output. See See “PSC Input Configuration” on page • Bit 3 – ...
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Bit 3 – PAOC1A : PSC 1 Asynchronous Output Control A When this bit is set, Fault input selected to block A can act directly to PSCOUT10 output. See Section “PSC Clock Sources”, page 161 • Bit 2 – ...
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Bit 2 – PARUN2 : PSC 2 Autorun When this bit is set, the PSC 2 starts with PSC1. That means that PSC 2 starts : • when PRUN1 bit in PCTL1 register is set, • or when PARUN1 ...
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Bit 3:0 – PRFMnx3:0: PSC n Fault Mode These four bits define the mode of operation of the Fault or Retrigger functions. (see PSC Functional Specification for more explanations) Table 16-17. Level Sensitivity and Fault Mode Operation PRFMnx3:0 0000b ...
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PSC 1 Input Capture Register – PICR1H and PICR1L Bit Read/Write Initial Value 16.25.18 PSC 2 Input Capture Register – PICR2H and PICR2L Bit Read/Write Initial Value • Bit 7 – PCSTn : PSC Capture Software Trig bit Set ...
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Bit 2 – POMV2A2: Output Matrix Output A Ramp 2 This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2 • Bit 1 – POMV2A1: Output Matrix Output A Ramp 1 This bit gives the state ...
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PSC1 Interrupt Flag Register – PIFR1 Bit Read/Write Initial Value 16.26.7 PSC2 Interrupt Flag Register – PIFR2 Bit Read/Write Initial Value • Bit 7 – POACnB : PSC n Output B Activity This bit is set by hardware each ...
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Bit 2:1 – PRNn1:0 : PSC n Ramp Number Memorization of the ramp number when the last PEVnA or PEVnB occured. Table 16-18. PSC n Ramp Number Description PRNn1 • Bit 0 – PEOPn: End ...
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Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM216/316 and peripheral devices or between several AVR devices. The AT90PWM216/316 SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous ...
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Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas- ter to Slave on the Master Out ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 17-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
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TABLE 2. Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for ...
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TABLE 2. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 17.2 SS Pin Functionality 17.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is ...
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Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the ...
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SPI Control Register – SPCR Bit Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the ...
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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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SPI Data Register – SPDR Bit Read/Write Initial Value • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to ...
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Figure 17-4. SPI Transfer Format with CPHA = 1 AT90PWM216/316 184 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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Figure 18-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation ...
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Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSEL bit in ...
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UMSEL, U2X and DDR_XCK bits. Table 18-1 ing the UBRR value for each mode of operation using an internally generated ...
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Note that to add some margin to avoid possible loss of data due to frequency variations. 18.3.4 Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or ...
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Figure 18-4. Frame Formats St ( IDLE be The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that ...
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Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC flag can be used to check that the Transmitter has completed all ...
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Data Transmission – USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by the ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following ...
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The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has ...
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The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be ...
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TABLE 2. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC0 rjmp USART_Receive ; Get status and 9th bit, then data from buffer lds lds r17, UCSRB lds r16, UDR ; If error, return -1 ...
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The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early ...
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Figure 18-5. Data OverRun example RxD DOR RxC Software Access to Receive buffer The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the ...
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TABLE 2. Assembly Code Example USART_Flush: C Code Example void USART_Flush( void ) { } Note: 18.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic ...
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Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the ...