AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 199

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

“Manual” mode
Detailed description
7707A–AVR–01/07
Example with 1 IN data bank
Example with 2 IN data banks
FIFOCON
FIFOCON
TXINI
TXINI
SW
SW
write data from CPU
write data from CPU
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO
and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is
composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON
bits are automatically updated by hardware regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
write data to the bank, and cleared by hardware when the bank is full.
The data are written by the CPU, following the next flow:
•
•
•
•
NAK
BANK 0
BANK 0
When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)
and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software
architecture choice,
The CPU acknowledges the interrupt by clearing TXINI,
The CPU can write the data into the current bank (write in UEDATX),
The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
•after “N” write into UEDATX
•as soon as RWAL is cleared by hardware.
SW
SW
IN
IN
SW
write data from CPU
BANK 1
(bank 0)
(bank 0)
DATA
DATA
SW
HW
HW
ACK
ACK
SW
SW
write data from CPU
write data from CPU
IN
BANK 0
BANK0
(bank 1)
DATA
SW
IN
ACK
199