AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 66

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AT90USB162-16MU

Manufacturer Part Number
AT90USB162-16MU
Description
MCU AVR USB 16K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheets

Specifications of AT90USB162-16MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFN
Controller Family/series
AVR USB
No. Of I/o's
22
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
16MHz
Rohs Compliant
Yes
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

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Switching Between
Input and Output
Reading the Pin Value
66
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as
a high-impedant environment will not notice the difference between a strong high driver and a
pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-
ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 26 summarizes the control signals for the pin value.
Table 26. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 29, the PINxn Register bit and the preceding latch consti-
tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay. Figure 30 shows a timing diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
Figure 30. Synchronization when Reading an Externally Applied Pin value
DDxn
0
0
0
1
1
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PORTxn
0
1
1
0
1
PINxn
r17
(in MCUCR)
PUD
X
X
X
0
1
pd,max
Output
Output
XXX
Input
Input
Input
I/O
and t
Pull-up
pd,min
Yes
No
No
No
No
t
pd, max
0x00
respectively.
XXX
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
t
pd, min
in r17, PINx
0xFF
7707A–AVR–01/07

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