ATMEGA165PV-8AUR Atmel, ATMEGA165PV-8AUR Datasheet - Page 19
ATMEGA165PV-8AUR
Manufacturer Part Number
ATMEGA165PV-8AUR
Description
MCU AVR 16KB FLASH 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165PV-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.3
6.3.1
8019K–AVR–11/10
EEPROM Data Memory
EEPROM Read/Write Access
Figure 6-3.
The ATmega165P contains 512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. This section describes the access between the EEPROM and
the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
“Serial Downloading” on page
“Parallel Programming Parameters, Pin Mapping, and Commands” on page 269
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
“Preventing EEPROM Corruption” on page 23
Address
clk
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
CC
is likely to rise or fall slowly on power-up/down. This causes the device for
Compute Address
279,
T1
Memory Access Instruction
“Programming via the JTAG Interface” on page
Address valid
Table 6-1 on page
T2
for details on how to avoid problems in
Next Instruction
T3
20. A self-timing function,
ATmega165P
respectively.
284, and
19
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