PIC18F6490-E/PT Microchip Technology, PIC18F6490-E/PT Datasheet - Page 12

• Manufacturer Part Number: PIC18F6490-E/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6490-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• For Use With: DM163028 - BOARD DEMO PICDEM LCD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC18F6390/6490/8390/8490
31. Module: Timer1
32. Module: MSSP
33. Module: MSSP
DS80207F-page 12
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
2. Use the internal clock synchronization option
Date Codes that pertain to this issue:
All engineering and production devices.
The MSSP configured in SPI slave mode will
generate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred
Reinitializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
(T1CON<7>).
by clearing the T1SYNC bit (T1CON<2>).
to the shift register
.
34. Module: MSSP
It has been observed that, following a Power-on
Reset, I
just configuring the SCL and SDA pins as either
inputs or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and cur-
rent range of the application's power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
1. Configure the SCL and SDA pins as outputs by
2. Force SCL and SDA low by clearing the
3. While keeping the LAT bits clear, configure
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.
clearing their corresponding TRIS bits.
corresponding LAT bits.
SCL and SDA as inputs by setting their TRIS
bits.
2
C™ mode may not initialize properly by
© 2007 Microchip Technology Inc.
2
C operation:
2
C