AT89LP6440-20MU Atmel, AT89LP6440-20MU Datasheet - Page 150
AT89LP6440-20MU
Manufacturer Part Number
AT89LP6440-20MU
Description
MCU 8051 64K FLASH ISP 44VQFN
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP6440-20MU.pdf
(194 pages)
Specifications of AT89LP6440-20MU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
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22.1.7
22.1.8
150
Description: The forty bits in the M register are shifted one bit to the left. Bit 0 is cleared. No flags are affected.
Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address
Operation: LSL
Operation: MOVC
Encoding:
Encoding:
AT89LP6440 - Preliminary
Function: Shift MAC Accumulator Left Logically
Function: Move code byte relative to Alternate Data Pointer
LSL M
MOVC A, @A+/DPTR
Example: The M register holds the value 0C5B1A29384H. The following instruction,
Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the
Cycles: 2
Cycles: 4
Bytes: 2
Bytes: 2
LSL M
leaves the M register holding the value 8B63452708H.
(M
(M
of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of the
unselected Data Pointer. The base register is not altered. Sixteen-bit addition is performed so a carry-out from
the low-order eight bits may propagate through higher-order bits. No flags are affected.
Accumulator to one of four values defined by the DB (define byte) directive.
TABLE:
If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator.
IF (DPS) = 0
THEN
ELSE
n+1
0
) ← 0
A5
A5
MOV
MOVC
RET
(A) ← ( (A) + (DPTR1) )
(A) ← ( (A) + (DPTR0) )
) ← (M
DB
DB
DB
DB
n
) n = 0 - 38
66H
/DPTR, #TABLE
A, @A+PC
77H
88H
99H
0
1
0
0
1
0
0
1
0
0
0
0
1
1
1
1
3706A–MICRO–9/09
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