PIC18F2221-I/ML Microchip Technology, PIC18F2221-I/ML Datasheet - Page 175

• Manufacturer Part Number: PIC18F2221-I/ML
• Description: IC PIC MCU FLASH 2KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/ML

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 17-5:
© 2007 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
SSPCON2: MSSP CONTROL REGISTER 2 (I
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT/ADMSK5: Acknowledge Data bit
In Master Receive mode:
1 = Not Acknowledge
0 = Acknowledge
In Slave mode:
1 = Address masking of ADD5 enabled
0 = Address masking of ADD5 disabled
ACKEN/ADMSK4: Acknowledge Sequence Enable bit
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
In Slave mode:
1 = Address masking of ADD4 enabled
0 = Address masking of ADD4 disabled
RCEN/ADMSK3: Receive Enable bit
In Master Receive mode:
1 = Enables Receive mode for I
0 = Receive Idle
In Slave mode:
1 = Address masking of ADD3 enabled
0 = Address masking of ADD3 disabled
PEN/ADMSK2: Stop Condition Enable bit
In Master mode:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
In Slave mode:
1 = Address masking of ADD2 enabled
0 = Address masking of ADD2 disabled
RSEN/ADMSK1: Repeated Start Condition Enable bit
In Master mode:
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
In Slave mode (7-bit Address mode):
1 = Address masking of ADD1 enabled
0 = Address masking of ADD1 disabled
In Slave mode (10-bit Address mode):
1 = Address masking of ADD1 and ADD0 enabled
0 = Address masking of ADD1 and ADD0 disabled
GCEN
R/W-0
Note:
Automatically cleared by hardware.
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
ACKSTAT
R/W-0
(1)
(1)
ADMSK5
(1)
(1)
ACKDT/
R/W-0
Preliminary
2
C
ACKEN
ADMSK4
R/W-0
PIC18F4321 FAMILY
(1)
/
RCEN
ADMSK3
2
R/W-0
C™ MODE)
(1)
/
ADMSK2
PEN
R/W-0
(1)
/
RSEN
ADMSK1
R/W-0
DS39689E-page 173
(1)
/
SEN
R/W-0
bit 0
(1)