DSPIC30F3012T-20E/ML Microchip Technology, DSPIC30F3012T-20E/ML Datasheet - Page 9

IC DSPIC MCU/DSP 24K 44QFN

DSPIC30F3012T-20E/ML

Manufacturer Part Number
DSPIC30F3012T-20E/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012T-20E/ML

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
XLT44QFN5 - SOCKET TRANS ICE 18DIP TO 44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
9. Module: ADC
10. Module: PLL
© 2010 Microchip Technology Inc.
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero. This means that if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
If 4x or 8x PLL mode is used, the input frequency
range is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
Work around
None. If 4x or 8x PLL mode is used, make sure the
input crystal or clock frequency is 5 MHz or
greater.
Affected Silicon Revisions
B0
B0
X
X
B1
B1
X
X
dsPIC30F3012/3013
DS80448D-page 9

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