DSPIC33FJ12MC202-I/SS Microchip Technology, DSPIC33FJ12MC202-I/SS Datasheet - Page 12
![IC DSPIC MCU/DSP 12K 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
DSPIC33FJ12MC202-I/SS
Manufacturer Part Number
DSPIC33FJ12MC202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ12MC202-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.6
3.6.1
The dsPIC33F/PIC24H devices have Configuration
bits stored in twelve 8-bit Configuration registers,
aligned on even configuration memory address
boundaries. These bits can be set or cleared to select
various device configurations. There are three types of
Configuration bits: system operation bits, code-protect
bits and unit ID bits. The system operation bits
determine the power-on settings for system level
TABLE 3-2:
DS70152H-page 12
RBS<1:0>
BSS<2:0>
Bit Field
Configuration Bits Programming
OVERVIEW
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION
Register
FBS
FBS
Boot Segment Data RAM Code Protection
11 = No RAM is reserved for Boot Segment
10 = Small-Sized Boot RAM
[128 bytes of RAM are reserved for Boot Segment]
01 = Medium-Sized Boot RAM
[256 bytes of RAM are reserved for Boot Segment]
00 = Large-Sized Boot RAM
[1024 bytes of RAM are reserved for Boot Segment]
Boot Segment Program Memory Code Protection
111 = No Boot Segment
110 = Standard security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x0007FF in other all other devices.]
101 = Standard security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x0007FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x001FFF in all other devices.]
100 = Standard security, Large-sized Boot Program Flash
[Boot Segment ends at 0x000FFF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x003FFF in all other devices.]
011 = No Boot Segment
010 = High security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.
Boot Segment ends at 0x0007FF in all other devices.]
001 = High security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x0007FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.
Boot Segment ends at 0x001FFF in all other devices.]
000 = High security, Large-sized Boot Program Flash
[Boot Segment ends at 0x000FFF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.
Boot Segment ends at 0x003FFF in all other devices.]
components, such as oscillator and Watchdog Timer.
The code-protect bits prevent program memory from
being read and written.
The register descriptions for the FBS, FSS, FGS,
FOSCSEL,
Configuration registers are shown in
Note 1: If any of the code-protect bits in FBS,
Description
FSS or FGS is clear, the entire device
must be erased before it can be
reprogrammed.
FOSC,
FWDT,
© 2010 Microchip Technology Inc.
FPOR
Table
and
3-2.
FICD