DSPIC33FJ12MC202-I/SS Microchip Technology, DSPIC33FJ12MC202-I/SS Datasheet - Page 26
![IC DSPIC MCU/DSP 12K 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
DSPIC33FJ12MC202-I/SS
Manufacturer Part Number
DSPIC33FJ12MC202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ12MC202-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
4.2.6
The READC command instructs the programming
executive to read N Configuration registers or Device
ID registers, starting from the 24-bit address specified
by Addr_MSB and Addr_LS. This command can only
be used to read 8-bit or 16-bit data.
When this command is used to read Configuration
registers, the upper byte in every data word returned by
the programming executive is 0x00 and the lower byte
contains the Configuration register value.
Expected Response (4 + 3 * (N
for N odd):
0x1100
2 + N
Configuration register or Device ID Register 1
...
Configuration register or Device ID Register N
DS70152H-page 26
15
Opcode
Length
N
Addr_MSB
Addr_LS
Note:
Opcode
Field
12 11
READC COMMAND
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
N
0x1
0x3
Number of 8-bit Configuration registers
or Device ID registers to read
(maximum of 256).
MSB of 24-bit source address.
Least Significant 16 bits of 24-bit
source address.
Addr_LS
8 7
Description
Length
–
1)/2 words
Addr_MSB
0
4.2.7
The READP command instructs the programming
executive to read N 24-bit words of code memory,
starting from the 24-bit address specified by Addr_MSB
and Addr_LS. This command can only be used to read
24-bit data. All data returned in the response to this
command uses the packed data format described in
Section 4.2.2 “Packed Data
Expected Response (2 + 3 * N/2 words for N even):
0x1200
2 + 3 * N/2
Least significant program memory word 1
...
Least significant data word N
Expected Response (4 + 3 * (N
for N odd):
0x1200
4 + 3 * (N
Least significant program memory word 1
...
MSB of program memory word N (zero padded)
15
Opcode
Length
N
Reserved
Addr_MSB
Addr_LS
Note:
Opcode
Field
Reserved
–
12 11
READP COMMAND
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
1)/2
0x2
0x4
Number of 24-bit instructions to read
(maximum of 32768).
0x0
MSB of 24-bit source address.
Least Significant 16 bits of 24-bit
source address.
Addr_LS
© 2010 Microchip Technology Inc.
8 7
N
Description
Format”.
Length
–
1)/2 words
Addr_MSB
0