PIC18F46J11-I/PT Microchip Technology, PIC18F46J11-I/PT Datasheet - Page 5

• Manufacturer Part Number: PIC18F46J11-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6. Module: Low-Power Modes (Deep Sleep)
EXAMPLE 2:
7. Module: DC Characteristics (Supply
 2010 Microchip Technology Inc.
EnterDeepSleep:
Entering Deep Sleep mode takes approximately
2 T
events that occur during this Deep Sleep entry
period may not generate a wake-up event.
Work around
If using the RTCC alarm for Deep Sleep wake-up,
code should only enter Deep Sleep mode when
the RTCC Value Registers Read Synchronization
bit (RTCCFG<4>) is clear.
This will prevent missing an RTCC alarm that
could occur during the period after the SLEEP
instruction, but before the Deep Sleep mode has
been fully entered.
Affected Silicon Revisions
The minimum operating voltage (V
(D001) for “F” devices is 2.25V. For “LF” devices
(such as the PIC18LF46J11), the minimum rated
V
Work around
None.
Affected Silicon Revisions
bsf
nop
sleep
(…)
goto
DD
A2
A2
X
X
CY
operating voltage is 2.0V.
, following the SLEEP instruction. Wake-up
A4
A4
X
DSCONH, DSEN
EnterDeepSleep
Voltage)
DEEP-SLEEP WAKE-UP WORK AROUND
; Enter Deep Sleep mode on SLEEP instruction
; Not compatible with A2 silicon
; Enter Deep Sleep mode
; Add code here to handle wake up events that may
; have been asserted prior to Deep Sleep entry
; re-attempt Deep Sleep entry if desired
DD
) parameter
PIC18F46J11 FAMILY
8. Module: Special Features (T1DIG)
The A4 revision silicon allows insertion of a
single instruction between setting the Deep
Sleep Enable bit (DSEN, DSCONH<7>) and
issuing the SLEEP instruction (see
The insertion of a NOP instruction before the
SLEEP instruction eliminates the 2 T
where wake-up events could be missed.
Before using this work around, users should
check their device’s revision ID bits to verify that
they have the A4 silicon. This can be done at run
time by a table read from address, 3FFFFEh.
On A2 revision silicon devices, the instruction
cannot be inserted between setting the DSEN
bit and executing the SLEEP instruction, or the
device will enter conventional Sleep mode, not
Deep Sleep.
On A4 silicon devices, if the firmware immedi-
ately executes SLEEP after setting DSEN, the
device will enter Deep Sleep mode without
benefitting from this work around.
The T1DIG Configuration bit (CONFIG2L<3>)
function is not implemented. Effectively, T1DIG is
‘0’ regardless of the value programmed into the bit.
Work around
None.
Affected Silicon Revisions
A2
X
A4
X
DS80435H-page 5
Example
CY
window
2).