PIC18F46J11-I/PT Microchip Technology, PIC18F46J11-I/PT Datasheet - Page 291

• Manufacturer Part Number: PIC18F46J11-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.5.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an inter-
rupt. It is possible to mask more than one address bit at
a time, which greatly expands the number of addresses
Acknowledged.
The I
masking is used or not. However, when address mask-
ing is used, the I
addresses and cause interrupts. When this occurs, it is
necessary to determine which address caused the
interrupt by checking SSPxBUF.
The PIC18F46J11 family of devices is capable of using
two different Address Masking modes in I
operation: 5-Bit Address Masking and 7-Bit Address
Masking. The Masking mode is selected at device
configuration using the MSSPMSK Configuration bit.
The default device configuration is 7-Bit Address
Masking.
Both Masking modes, in turn, support address masking
of 7-bit and 10-bit addresses. The combination of
Masking modes and addresses provide different
ranges of Acknowledgable addresses for each
combination.
While both Masking modes function in roughly the
same manner, the way they use address masks is
different.
18.5.3.3
As the name implies, 5-Bit Address Masking mode uses
an address mask of up to five bits to create a range of
addresses to be Acknowledged, using bits 5 through 1 of
EXAMPLE 18-3:
© 2009 Microchip Technology Inc.
7-Bit Addressing:
10-Bit Addressing:
2
C slave behaves the same way, whether address
SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPxADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
Address Masking Modes
5-Bit Address Masking Mode
2
C slave can Acknowledge multiple
ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE
2
C slave
PIC18F46J11 FAMILY
the incoming address. This allows the module to
Acknowledge up to 31 addresses when using 7-bit
addressing, or 63 addresses with 10-bit addressing (see
Example 18-3). This Masking mode is selected when
the MSSPMSK Configuration bit is programmed (‘0’).
The address mask in this mode is stored in the
SSPxCON2 register, which stops functioning as a control
register in I
Address
ADMSK<5:1>
corresponding address bits in the SSPxADD register. For
any ADMSK bits that are set (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPxADD<n> = x).
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have an
active address mask.
In 10-Bit Address Masking mode, bits, ADMSK<5:2>,
mask the corresponding address bits in the SSPxADD
register. In addition, ADMSK1 simultaneously masks
the two LSbs of the address (SSPxADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the cor-
responding address bit is ignored (SPxADD<n> = x).
Also note, that although in 10-Bit Address Masking
mode, the upper address bits reuse part of the
SSPxADD register bits. The address mask bits do not
interact with those bits; they only affect the lower
address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two MSbs of the address are not
Masking
2
bits of the address.
affected by address masking.
C Slave mode (Register 18-8). In 7-Bit
(SSPxCON2<5:1>),
mode,
address
DS39932C-page 291
mask
mask
bits,
the