DSPIC30F3011T-20E/PT Microchip Technology, DSPIC30F3011T-20E/PT Datasheet - Page 14

• Manufacturer Part Number: DSPIC30F3011T-20E/PT
• Description: IC DSPIC MCU/DSP 24K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011T-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3010/3011
18. Module: I/O Port – Port Pin Multiplexed
19. Module: ADC Offset Error When Using
20. Module: Motor Control PWM – PWM
21. Module: I
DS80216K-page 14
If the user application enables the auto-baud
feature in the UART module, the I/O pin
multiplexed with the IC1 (Input Capture) pin cannot
be used as a digital input.
Work around
None.
If the user application uses the internal reference
voltage (AV
greater than what is specified in the device data
sheet.
Work around
As an alternative, use the external reference
voltage (V
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up as if PTDIR was zero.
Work around
None.
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are
configured for 10-bit addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
2
C devices, the addresses as well as bits
REF
with IC1
Internal Reference (AV
Counter Register
DD
2
C
-, V
, AV
REF
2
SS
C devices on the bus, one of
), the ADC has an offset error
+).
DD
, AV
SS
)
22. Module: Timer
23. Module: PLL Lock Status Bit
24. Module: PSV Operations
When the timer is being operated in the
asynchronous
oscillator (32.768 kHz) and the device is put into
Sleep mode, a clock switch to any other oscillator
mode before putting the device to Sleep prevents
the timer from waking the device from Sleep.
Work around
Do not clock switch to any other oscillator mode if
the timer is being used in the asynchronous mode
using the secondary oscillator (32.768 kHz).
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
Work around
The user application must include an oscillator
failure trap service routine. In the trap service
routine, first inspect the status of the Clock Failure
Status bit (OSCCON<3>). If this bit is clear, return
from the trap service routine immediately and
continue program execution.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register indirect addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
mode) with pre/post-decrement
mode
© 2008 Microchip Technology Inc.
using
the
secondary