PIC18F8410-E/PT Microchip Technology, PIC18F8410-E/PT Datasheet - Page 54
PIC18F8410-E/PT
Manufacturer Part Number
PIC18F8410-E/PT
Description
IC PIC MCU FLASH 16KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
Specifications of PIC18F8410-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8410-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6310/6410/8310/8410
TABLE 4-2:
DS39635C-page 54
Note 1:
Primary Device Clock
T1OSC or INTRC
(PRI_IDLE mode)
Before Wake-up
2:
3:
4:
5:
Clock Source
(Sleep mode)
INTOSC
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
with any other required delays (see
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
also designated as T
Execution continues during T
None
CSD
OST
(Parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
is the Oscillator Start-up Timer (Parameter 32). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
(1)
PLL
.
EC, RC, INTRC
EC, RC, INTRC
EC, RC, INTRC
EC, RC, INTRC
After Wake-up
Clock Source
IOBST
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
HSPLL
HSPLL
HSPLL
HSPLL
(Parameter 39), the INTOSC stabilization period.
Section 4.4 “Idle
(3)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
rc
Modes”).
is the PLL Lock-out Timer (Parameter F12); it is
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST
None
CSD
CSD
CSD
CSD
OST
OST
OST
+ t
+ t
+ t
(4)
(5)
(4)
(2)
(2)
(2)
(2)
rc
(5)
rc
rc
(5)
(4)
(4)
(4)
2010 Microchip Technology Inc.
Clock Ready Status Bit
(OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
—
—
—
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