PIC18F1330-I/P Microchip Technology, PIC18F1330-I/P Datasheet - Page 309
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PIC18F1330-I/P
Manufacturer Part Number
PIC18F1330-I/P
Description
IC PIC MCU FLASH 4KX16 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1220-ISO.pdf
(36 pages)
4.PIC18F1230-ISO.pdf
(6 pages)
5.PIC18F1230-ISO.pdf
(12 pages)
6.PIC18F1230-ISO.pdf
(4 pages)
7.PIC18F1230-IP.pdf
(312 pages)
Specifications of PIC18F1330-I/P
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
18PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F1330-I/P
Manufacturer:
VISHAY
Quantity:
12 000
Part Number:
PIC18F1330-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Extended Instruction Set
External Clock Input ........................................................... 22
F
Fail-Safe Clock Monitor ............................................ 191, 205
Fast Register Stack ............................................................ 54
Firmware Instructions ....................................................... 215
Flash Program Memory ..................................................... 71
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 236
H
Hardware Multiplier ............................................................ 85
2009 Microchip Technology Inc.
Synchronous Slave Mode ........................................ 167
ADDFSR .................................................................. 258
ADDULNK ................................................................ 258
and Using MPLAB Tools .......................................... 264
CALLW ..................................................................... 259
Considerations for Use ............................................ 262
MOVSF .................................................................... 259
MOVSS .................................................................... 260
PUSHL ..................................................................... 260
SUBFSR .................................................................. 261
SUBULNK ................................................................ 261
Syntax ...................................................................... 257
Exiting Operation ..................................................... 205
Interrupts in Power-Managed Modes ....................... 206
POR or Wake From Sleep ....................................... 206
WDT During Oscillator Failure ................................. 205
Associated Registers ................................................. 79
Control Registers ....................................................... 72
Erase Sequence ........................................................ 76
Erasing ....................................................................... 76
Operation During Code-Protect ................................. 79
Reading ...................................................................... 75
Table Pointer
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Write Sequence ......................................................... 77
Writing ........................................................................ 77
Introduction ................................................................ 85
Operation ................................................................... 85
Performance Comparison .......................................... 85
Associated Registers, Transmit ....................... 165
Reception ......................................................... 166
Transmission ................................................... 164
Associated Registers, Receive ........................ 168
Associated Registers, Transmit ....................... 167
Reception ......................................................... 168
Transmission ................................................... 167
EECON1 and EECON2 ..................................... 72
TABLAT (Table Latch) Register ......................... 74
TBLPTR (Table Pointer) Register ...................... 74
Boundaries Based on Operation ........................ 74
Operations with TBLRD and TBLWT (table) ...... 74
Protection Against Spurious Writes ................... 79
Unexpected Termination .................................... 79
Write Verify ........................................................ 79
I
I/O Ports ............................................................................ 87
ID Locations ............................................................. 191, 210
INCF ................................................................................ 236
INCFSZ ............................................................................ 237
In-Circuit Debugger .......................................................... 210
In-Circuit Serial Programming (ICSP) ...................... 191, 210
Independent PWM Mode
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 262
Indirect Addressing ............................................................ 66
INFSNZ ............................................................................ 237
Initialization Conditions for all Registers ...................... 47–50
Instruction Cycle ................................................................ 55
Instruction Set .................................................................. 215
Duty Cycle Assignment ........................................... 137
Output ...................................................................... 137
Output, Channel Override ........................................ 138
and Standard PIC18 Instructions ............................. 262
Clocking Scheme ....................................................... 55
Flow/Pipelining .......................................................... 55
ADDLW .................................................................... 221
ADDWF ................................................................... 221
ADDWF (Indexed Literal Offset Mode) .................... 263
ADDWFC ................................................................. 222
ANDLW .................................................................... 222
ANDWF ................................................................... 223
BC ............................................................................ 223
BCF ......................................................................... 224
BN ............................................................................ 224
BNC ......................................................................... 225
BNN ......................................................................... 225
BNOV ...................................................................... 226
BNZ ......................................................................... 226
BOV ......................................................................... 229
BRA ......................................................................... 227
BSF .......................................................................... 227
BSF (Indexed Literal Offset Mode) .......................... 263
BTFSC ..................................................................... 228
BTFSS ..................................................................... 228
BTG ......................................................................... 229
BZ ............................................................................ 230
CALL ........................................................................ 230
CLRF ....................................................................... 231
CLRWDT ................................................................. 231
COMF ...................................................................... 232
CPFSEQ .................................................................. 232
CPFSGT .................................................................. 233
CPFSLT ................................................................... 233
DAW ........................................................................ 234
DCFSNZ .................................................................. 235
DECF ....................................................................... 234
DECFSZ .................................................................. 235
Extended Instruction Set ......................................... 257
General Format ....................................................... 217
GOTO ...................................................................... 236
INCF ........................................................................ 236
INCFSZ .................................................................... 237
INFSNZ .................................................................... 237
IORLW ..................................................................... 238
IORWF ..................................................................... 238
LFSR ....................................................................... 239
MOVF ...................................................................... 239
MOVFF .................................................................... 240
MOVLB .................................................................... 240
PIC18F1230/1330
DS39758D-page 309