DSPIC30F2011-30I/ML Microchip Technology, DSPIC30F2011-30I/ML Datasheet
DSPIC30F2011-30I/ML
Specifications of DSPIC30F2011-30I/ML
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DSPIC30F2011-30I/ML Summary of contents
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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70139G ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • Single-cycle ±16 shift © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K Pin Diagrams 18-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC ...
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... Pin Diagrams (1) 28-Pin QFN-S AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 15 externally. SS DS70139G-page 5 ...
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... Pin Diagrams (1) 28-Pin QFN-S AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70139G-page AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 19 CN17/RF4 dsPIC30F2012 4 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 externally. SS © 2010 Microchip Technology Inc. ...
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... Pin Diagram (1) 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3012 OSC2/CLKO/RC15 32 OSC1/CLKI AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 externally. SS DS70139G-page 7 ...
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... Pin Diagrams (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70139G-page dsPIC30F3013 OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 externally. SS © 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 to receive the most current information on all of our products. DS70139G-page 9 ...
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... NOTES: DS70139G-page 10 © 2010 Microchip Technology Inc. ...
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... MCU and DSC Programmer’s Reference (DS70157). This data sheet contains information specific to the dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and dsPIC30F3013 Digital Signal Controllers (DSC). These devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. ...
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... FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (12 Kbytes) Data Latch 16 ROM Latch 24 16 Instruction Decode & Control Power-up ...
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... Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (512 bytes) (512 bytes) 16 Address Address Latch Latch RAGU ...
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... FIGURE 1-3: dsPIC30F3012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... Timing Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch Latch RAGU Y AGU ...
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... Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... Schmitt Trigger input with CMOS levels I = Input © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Synchronous serial clock input/output for I Synchronous serial data input/output for I 32 kHz low-power oscillator crystal output. 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. ...
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... NOTES: DS70139G-page 18 © 2010 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes and most instructions can address data either as words or bytes. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of ...
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... The core does not support a multi-stage instruction pipeline. However, a single-stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 Program Space Visibility Page Address ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide opera- tions, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF - 16/16 signed fractional divide 2 ...
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... • y MPY A = – x • y MPY – x • y MSC © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has several options selected through various bits in the CPU Core Configuration register (CORCON), which are: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139G-page 24 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2010 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled through the barrel shifter prior to accumulation. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated if saturation is enabled. When satura- ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70139G-page 28 © 2010 Microchip Technology Inc. ...
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... The program address space is 4M instruction words. The program space memory maps dsPIC30F2011/2012/3012/3013 devices is shown in Figure 3-1. Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by ...
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... FIGURE 3-1: PROGRAM SPACE MEMORY MAPS dsPIC30F2011/2012 Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (4K instructions) Reserved (Read ‘0’s) Reserved UNITID (32 instr.) Reserved Device Configuration Registers Reserved DEVID (2) DS70139G-page 30 000000 ...
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... Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24-bit wide program memory. Consequently, instructions are always However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn<0> ...
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... FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space 15 EA<15> Data Space 15 EA EA<15> Upper Half of Data Space is Mapped into Program Space BSET CORCON,#2 ; Set PSV bit MOV #0x0 Set PSVPAG register MOV W0, PSVPAG MOV 0x9200 Access program memory location ...
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... W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in ...
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... FIGURE 3-7: dsPIC30F3012/3013 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 2 Kbyte 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70139G-page 36 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 SFR SPACE ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... MSB is always clear. Note push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 3-10: 0x0000 15 000000000 There is a Stack Pointer Limit register (SPLIM) associated with uninitialized at Reset ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70139G-page 42 © 2010 Microchip Technology Inc. ...
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... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by instructions, move and accumulator instructions also support Register Indirect with Register Addressing mode, also referred to as Register Indexed mode ...
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... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control registers: register, MODCON<15:0>, contains enable flags as well register field to specify the W address registers ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to) ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... NOTES: DS70139G-page 48 © 2010 Microchip Technology Inc. ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, the ...
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... LOADING WRITE LATCHES Example 5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 5-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70139G-page 54 © 2010 Microchip Technology Inc. ...
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... The write typically requires complete, but the write time varies with voltage and temperature. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is responsible for waiting for the appropriate duration of time before initiating another data EEPROM write/ erase operation ...
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... Erasing Data EEPROM 6.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EXAMPLE 6-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV #data2,W2 TBLWTL W2 [ W0]++ , MOV #data3,W2 TBLWTL W2 [ W0]++ , MOV #data4,W2 TBLWTL W2 [ W0]++ , MOV #data5,W2 TBLWTL W2 [ W0]++ , MOV #data6,W2 TBLWTL W2 [ W0]++ , MOV #data7,W2 TBLWTL W2 [ W0]++ ...
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... WR Port Read LAT Read Port © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). Any bit and its associated data and Control registers that are not valid for a particular device are disabled ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (V converted ...
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... PORTC 02CE RC15 RC14 RC13 — LATC 02D0 LATC15 LATC14 LATC13 — Legend: — = unimplemented bit, read as ‘0’ TABLE 7-4: PORTD REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 02D2 — — — — PORTD 02D4 — ...
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... LATF 02E2 — — — — Legend: — = unimplemented bit, read as ‘0’ Note: The dsPIC30F2011/3012 devices do not have TRISF, PORTF, or LATF. Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 — — TRISD9 TRISD8 — — — — ...
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... There are external signals (CN0 through CN7, CN17 and CN18) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 7-7: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2011/3012 (BITS 7-0) SFR Address Bit 7 Bit 6 ...
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... NOTES: DS70139G-page 64 © 2010 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions ...
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... UART2 Transmitter 26-41 34-49 Reserved 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority Note 1: Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. © 2010 Microchip Technology Inc. ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously causes a Reset. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
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... The processor then loads the priority level for this interrupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine (ISR). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x0000 15 0x000002 0x000004 SRL IPL3 PC< ...
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... Fast Context Saving A context saving option is available using shadow registers. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only ...
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... TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 — — — ...
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TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... SOSCO/ T1CK LPOSCEN SOSCI © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value preloaded into the Period register PR1, then resets to ‘ ...
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... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit, TGATE (T1CON<6>), must be set to enable this mode. ...
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... Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the interrupt controller. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139G-page 75 ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer ...
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... These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 For 32-bit timer/counter operation, Timer2 is the ls word and Timer3 is the ms word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70139G-page 78 ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 TGATE ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70139G-page 82 © 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels. 11.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — Legend uninitialized bit; — = ...
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... NOTES: DS70139G-page 86 © 2010 Microchip Technology Inc. ...
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... Output Compare During Sleep and Idle modes • Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OC1CON and OC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have 2 compare channels. OCxRS and OCxR in Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 12.2 Simple Output Compare Match Mode When control bits OCM< ...
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... Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set. ...
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... Output Compare Operation During CPU Sleep Mode When the CPU enters Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel drives the pin to the active state that was observed prior to entering the CPU Sleep state ...
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TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Legend: ...
Page 92
... NOTES: DS70139G-page 92 © 2010 Microchip Technology Inc. ...
Page 93
... It communicating with other peripheral devices, such as EEPROMs, shift registers, display drivers and A/D converters, or other microcontrollers compatible with Motorola's SPI and SIOP interfaces. The dsPIC30F2011/2012/3012/3013 devices feature one SPI module, SPI1. 13.1 Operating Function Description Figure 13 simplified block diagram of the SPI ...
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... FIGURE 13-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDI1 bit 0 SDO1 SS & FSYNC Control SS1 SCK1 Figure 13-2 depicts the a master/slave connection between two processors. In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPI1BUF. ...
Page 95
... CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SDO1 SDI1 SDI1 SDO1 MSb Serial Clock ...
Page 96
TABLE 13-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, read ...
Page 97
... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
Page 98
... FIGURE 14-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70139G-page 98 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
Page 99
... ACK received from the master. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 100
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 14.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 101
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support As a master device, six operations are supported: ...
Page 102
... I C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (I2CCON<3>). The I module must be Idle before the RCEN bit is set, otherwise the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin ACK and data are shifted into the I2CRSR on the rising edge of each clock ...
Page 103
TABLE 14- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...
Page 104
... NOTES: DS70139G-page 104 © 2010 Microchip Technology Inc. ...
Page 105
... Family Reference Manual” (DS70046). This section describes the Universal Asynchronous Receiver/Transmitter Communications module. The dsPIC30F2011/2012/3012 processors have one UART module (UART1). The dsPIC30F3013 processor has two UART modules (UART1 and UART2). FIGURE 15-1: UART TRANSMITTER BLOCK DIAGRAM ...
Page 106
... FIGURE 15-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70139G-page 106 Internal Data Bus 16 Write Read URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 107
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 108
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 109
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...
Page 110
... UART Operation During CPU Sleep and Idle Modes 15.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shut down and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘ ...
Page 111
... U2BRG 021E Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: UART2 is not available on dsPIC30F2011/2012/3012 devices. 2: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 — ALTIO — ...
Page 112
... NOTES: DS70139G-page 112 © 2010 Microchip Technology Inc. ...
Page 113
... AN7 1000 AN8 1001 AN9 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 114
... A/D Result Buffer The module contains a 16-word dual port read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data formats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 115
... EQUATION 16-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “Electrical Characteristics” ...
Page 116
... ADC and the required operating conditions. Figure 16-2 depicts the recommended circuit for the conversion rates above 200 ksps. The dsPIC30F2011 is shown as an example. TABLE 16-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-bit ADC Conversion Rates ...
Page 117
... Note: C value depends on device package and is not tested. Effect of C PIN © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The following figure shows the timing diagram of the ADC running at 200 ksps. The T conjunction with the guidelines described above allows a conversion speed of 200 ksps. See code example ...
Page 118
... Module Power-Down Modes The module has two internal power modes. When the ADON bit is ‘1’, the module is in Active mode fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings ...
Page 119
... ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16.14 Connection Considerations The analog inputs have diodes to V protection. This requires that the analog input be have ...
Page 120
... TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ADCBUF4 0288 — ...
Page 121
TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...
Page 122
... NOTES: DS70139G-page 122 © 2010 Microchip Technology Inc. ...
Page 123
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 124
... TABLE 17-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2. XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 125
... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector Oscillator Start-up ...
Page 126
... Oscillator Configurations 17.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, b) and FPR<4:0> Configuration bits that select one of 15 oscillator choices within the primary group. ...
Page 127
... The tuning step size is an approximation and is neither characterized nor tested. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, a PLL multiplier (respectively) is applied. Note: ...
Page 128
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, ...
Page 129
... DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.3.1 POR: POWER-ON RESET A power-on event will generate an internal POR pulse devices when a V rise is detected. The Reset pulse will occur DD at the POR circuit threshold voltage (V nominally 1 ...
Page 130
... FIGURE 17-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 131
... Specifications in the specific device data sheet for BOR voltage limit specifications. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device Configuration bit values (FOS<2:0> and FPR< ...
Page 132
... Table 17-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column. TABLE 17-5: ...
Page 133
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV; ...
Page 134
... Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The Sleep Status bit in the RCON register is set upon wake-up. ...
Page 135
... Control reg- isters are already configured to enable module operation dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2010 Microchip Technology Inc. ...
Page 136
TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP SFR Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> OSCTUN 0744 — — — — PMD1 0770 — — T3MD ...
Page 137
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 138
... All instructions are a single word, except for certain double-word instructions, which double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
Page 139
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description DS70139G-page 139 ...
Page 140
... TABLE 18-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 141
... DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 142
... TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 143
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 144
... TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd ...
Page 145
... Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 146
... MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
Page 147
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
Page 148
... PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
Page 149
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) ..................................... -0. .......................................................................................................... ± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latch-up dsPIC30F2011/2012/3012/3013 Sensor Family + 0.3V) DD pin, rather PP Table 20-2 for P . DMAX table on page 4 of DS70139G-page 149 ...
Page 150
... DC Characteristics TABLE 20-1: OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C TABLE 20-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F201x-30I dsPIC30F301x-30I Operating Junction Temperature Range ...
Page 151
... Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max 2.5 — ...
Page 152
... TABLE 20-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC31a 1.6 3.0 DC31b 1.6 3.0 DC31c 1.6 3.0 DC31e 3.6 6.0 DC31f 3.3 6.0 DC31g 3.2 6.0 DC30a 3.0 5.0 DC30b 3.0 5.0 DC30c 3.1 5.0 DC30e 6 ...
Page 153
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 154
... TABLE 20-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60a 0.3 — DC60b 1.3 30.0 DC60c 16.0 60.0 DC60e 0.5 — DC60f 3.7 45.0 DC60g 25.0 90.0 DC61a 6.0 9.0 DC61b 6.0 9.0 DC61c 6.0 9.0 DC61e 13 ...
Page 155
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
Page 156
... TABLE 20-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO ( Osc mode) V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO ( Osc mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...
Page 157
... External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — ...
Page 158
... FIGURE 20-2: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) RESET (due to BOR) TABLE 20-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. (2) BO10 V BOR Voltage BOR V transition high to DD low BO15 V BHYS Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 159
... EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 160
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 20-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 20-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 — for all pins except OSC2 ...
Page 161
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 162
... TABLE 20-15: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 163
... TABLE 20-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 ...
Page 164
... FIGURE 20-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 20-3 for load conditions. TABLE 20-20: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 165
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 20-2 and Table 20-11 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Note: Refer to Figure 20-3 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 166
... FIGURE 20-7: BAND GAP START-UP TIME CHARACTERISTICS 0V Enable Band Gap (see Note) Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set. TABLE 20-22: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 167
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature Min Typ Synchronous, 0 ...
Page 168
... TABLE 20-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer2 and Timer4 are Type B ...
Page 169
... TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IC10 IC11 IC15 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 170
... FIGURE 20-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) Note: Refer to TABLE 20-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC10 TccF OCx Output Fall Time OC11 TccR OCx Output Rise Time Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 171
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 172
... FIGURE 20-12: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb IN SP40 SP41 Note: Refer to Figure 20-3 for load conditions. TABLE 20-29: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
Page 173
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP35 SP20 LSb BIT BIT ...
Page 174
... FIGURE 20-14: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 Note: Refer to Figure 20-3 for load conditions. TABLE 20-31: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP35 SP72 SP52 BIT LSb SP30,SP31 BIT LSb IN SP52 SP72 SP73 SP51 DS70139G-page 175 ...
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... TABLE 20-32: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TscL SP70 SCK Input Low Time X SP71 TscH SCK Input High Time X SP72 TscF SCK Input Fall Time X SP73 TscR SCK Input Rise Time X SP30 TdoF SDO ...
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... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 DS70139G-page 177 ...
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... I TABLE 20-33: I C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol Characteristic No. IM10 T : Clock Low Time 100 kHz mode LO SCL 400 kHz mode 1 MHz mode IM11 T : Clock High Time 100 kHz mode HI SCL 400 kHz mode 1 MHz mode ...
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... IS21 T : SDA and SCL R SCL Rise Time Note 1: Maximum pin capacitance = 10 pF for all I © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IS11 IS10 IS26 IS25 IS40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
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... TABLE 20-34: C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED CHARACTERISTICS Param Symbol Characteristic No. IS25 T : Data Input SU DAT Setup Time IS26 T : Data Input HD DAT Hold Time IS30 T : Start Condition SU STA Setup Time IS31 T : Start Condition HD STA Hold Time IS33 T : Stop Condition ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
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... TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol Characteristic No. AD01 AV Module V Supply DD DD AD02 AV Module V Supply SS SS AD05 V Reference Voltage High REFH AD06 V Reference Voltage Low REFL AD07 V Absolute Reference REF Voltage AD08 I Current Drain REF AD10 V -V Full-Scale Input Span ...
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... Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external V © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min. ...
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... FIGURE 20-21: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Set SAMP Clear SAMP Execution SAMP ch0_dischrg ch0_samp eoc AD61 AD60 T SAMP DONE ADIF ADRES( Software sets ADCON. SAMP to start sampling Sampling starts after discharge period described in Section 18. “12-bit A/D Converter” in the dsPIC30F Family Reference Manual (DS70046). ...
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... ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). DPU During this time the ADC result is indeterminate. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature-40°C ≤ T Min. Typ Max ...
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... NOTES: DS70139G-page 186 © 2010 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 e 30I/SO 0610017 Example dsPIC30F2012 30I/ ...
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... Package Marking Information (Continued) 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN-S XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139G-page 188 Example dsPIC30F3013 e 3 30I/SO 0610017 Example 30F2011 e 30I/MM 3 0610017 Example dsPIC 30F3013 e 30I/ML 3 0610017 © 2010 Microchip Technology Inc. ...
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... N NOTE © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139G-page 189 ...
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... D N NOTE DS70139G-page 190 α φ A2 β © 2010 Microchip Technology Inc. ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139G-page 191 ...
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... N NOTE DS70139G-page 192 © 2010 Microchip Technology Inc. c ...
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... N NOTE © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 α φ β DS70139G-page 193 ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70139G-page 194 © 2010 Microchip Technology Inc. ...
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... D TOP VIEW A3 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED PAD NOTE 1 BOTTOM VIEW DS70139G-page 195 ...
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... DS70139G-page 196 © 2010 Microchip Technology Inc. ...
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... D TOP VIEW A3 © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED PAD NOTE BOTTOM VIEW DS70139G-page 197 ...
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... DS70139G-page 198 © 2010 Microchip Technology Inc. ...
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... Table 20-21) Revision E (December 2006) This revision includes updates to the packaging diagrams. © 2010 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Revision F (May 2008) This revision reflects these updates: • Added FUSE Configuration Register (FICD) details (see Registers” • Added Note 2 to Device Configuration Registers ...
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... Revision G (November 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name “High-Performance, 16-Bit Digital Signal Controllers” Section 1.0 “Device Overview” ...