DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 18
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DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
TABLE 3-7:
TABLE 3-8:
DS70152H-page 18
0xF80000 FBS
0xF80002 RESERVED
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
Address
Address
2:
2:
3:
4:
These bits are reserved (read as ‘1’) and must be programmed as ‘1’.
The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL
ICE in-circuit emulator clear this bit by default when connecting to a device.
This Configuration register is not available and reads as 0xFF on dsPIC33FJ32GP302/304 devices.
These bits are reserved and always read as ‘1’.
These bits are reserved (read as ‘1’) and must be programmed as ‘1’.
The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL
ICE in-circuit emulator clear this bit by default when connecting to a device.
Name
Name
(1)
dsPIC33FJ32MC202/204 AND dsPIC33FJ16MC304 DEVICE CONFIGURATION
REGISTER MAP
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 AND dsPIC33FJ128GPX02/X04,
AND PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
DEVICE CONFIGURATION REGISTER MAP
FWDTEN WINDIS
FWDTEN WINDIS
PWMPIN
IESO
IESO
Bit 7
Bit 7
FCKSM<1:0>
FCKSM<1:0>
—
—
—
—
Reserved
Reserved
RBS<1:0>
RSS<1:0>
Reserved
HPOL
Bit 6
Bit 6
(1)
(3)
—
—
—
—
—
—
(2)
JTAGEN
JTAGEN
IOL1WAY
IOL1WAY
LPOL
Bit 5
Bit 5
—
—
—
—
—
—
—
—
—
—
(2)
(4)
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
WDTPRE
ALTI2C
ALTI2C
Bit 4
Bit 4
—
—
—
—
—
—
—
—
—
—
—
—
Bit 3
Bit 3
—
—
—
—
—
—
—
—
—
BSS<2:0>
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
OSCIOFNC POSCMD<1:0>
© 2010 Microchip Technology Inc.
WDTPOST<3:0>
WDTPOST<3:0>
Bit 2
Bit 2
—
—
—
GSS<1:0>
GSS<1:0>
FPWRT<2:0>
FPWRT<2:0>
FNOSC<2:0>
FNOSC<2:0>
Bit 1
Bit 1
—
ICS<1:0>
ICS<1:0>
GWRP
GWRP
BWRP
BWRP
SWRP
Bit 0
Bit 0
—