PIC16C63A-20E/SS Microchip Technology, PIC16C63A-20E/SS Datasheet - Page 67

• Manufacturer Part Number: PIC16C63A-20E/SS
• Description: IC MCU OTP 4KX14 PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-20E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

11.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 11-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
TABLE 11-1:
TABLE 11-2:
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Address
2000 Microchip Technology Inc.
SYNC
98h
18h
99h
0
1
USART Baud Rate Generator
(BRG)
SPBRG
RCSTA
TXSTA
Name
(Asynchronous) Baud Rate = F
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Synchronous) Baud Rate = F
Baud Rate Generator register
CSRC
SPEN
Bit 7
BRGH = 0 (Low Speed)
Bit 6
RX9
TX9
SREN
TXEN
Bit 5
CREN
SYNC
OSC
OSC
Bit 4
/(64(SPBRG+1))
/(4(SPBRG+1))
PIC16C63A/65B/73B/74B
Bit 3
—
—
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
11.1.1
The data on the RC7/RX/DT pin is sampled three times
near the center of each bit time by a majority detect cir-
cuit to determine if a high or a low level is present at the
RX pin.
BRGH
FERR
Bit 2
OERR
TRMT
Bit 1
SAMPLING
OSC
Baud Rate = F
/(16(X + 1)) equation can reduce the
RX9D
TX9D
Bit 0
BRGH = 1 (High Speed)
0000 -010
0000 -00x
0000 0000
Value on:
POR,
OSC
BOR
N/A
/(16(SPBRG+1))
DS30605C-page 67
0000 -010
0000 -00x
0000 0000
Value on
RESETS
all other