AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 80
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AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
10.1.4
10.1.5
10.1.6
10.1.7
32099F–11/2010
SCIF
AST
WDT
GPIO
3. Sleepwalking in Idle and Frozen Sleep mode will mask all other PB clocks
1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
1. Reset may set status bits in the AST
2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
1. Clearing GPIO interrupt may fail
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
If the CPU is in Idle or Frozen Sleep mode and a module is in a state that triggers sleep
walking, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into Idle or frozen mode.
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures.
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.
If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may
be set.
Fix/Workaround
If the part is reset and the AST is used, clear all bits in the Status Register (SR) before enter-
ing sleep mode.
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is
enabled for the corresponding port.
AT32UC3L016/32/64
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