ATMEGA644PV-10PQ Atmel, ATMEGA644PV-10PQ Datasheet - Page 22
![MCU AVR 64K FLASH 10MHZ 40-PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644PV-10PQ
Manufacturer Part Number
ATMEGA644PV-10PQ
Description
MCU AVR 64K FLASH 10MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10PQ
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5.5
8011O–AVR–07/10
I/O Memory
The I/O space definition of the ATmega164P/324P/644P is shown in
page
All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations
may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between
the 32 general purpose working registers and the I/O space. I/O Registers within the address
range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis-
ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN and OUT,
the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space
u s i n g L D a n d S T i n s t r u c t i o n s , 0 x 2 0 m u s t b e a d d e d t o t h e s e a d d r e s s e s . T h e
ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-
tions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega164P/324P/644P contains three General Purpose I/O Registers, see
Description” on page
particularly useful for storing global variables and Status Flags. General Purpose I/O Registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions.
413.
23. These registers can be used for storing any information, and they are
ATmega164P/324P/644P
”Register Summary” on
”Register
22
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