ATMEGA644PV-10PQ Atmel, ATMEGA644PV-10PQ Datasheet - Page 275
![MCU AVR 64K FLASH 10MHZ 40-PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644PV-10PQ
Manufacturer Part Number
ATMEGA644PV-10PQ
Description
MCU AVR 64K FLASH 10MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10PQ
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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22.8
22.8.1
22.8.2
8011O–AVR–07/10
Register Description
MCUCR – MCU Control Register
MCUSR – MCU Status Register
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x34 (0x54)
Read/Write
Initial Value
JTD
R/W
7
0
R
7
–
0
BODS
R
6
0
R
6
–
0
BODSE
R
5
0
R
5
–
0
JTRF
PUD
R/W
R/W
4
0
4
ATmega164P/324P/644P
WDRF
R/W
R
3
–
0
3
See Bit Description
BORF
R/W
R
2
–
0
2
EXTRF
IVSEL
R/W
R/W
1
0
1
PORF
IVCE
R/W
R/W
0
0
0
MCUCR
MCUSR
275
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