DSPIC30F4013T-20E/ML Microchip Technology, DSPIC30F4013T-20E/ML Datasheet - Page 8

• Manufacturer Part Number: DSPIC30F4013T-20E/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20E/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3014/4013
5. Module: CPU
DS80455D-page 8
When a user executes a DISI #7, for example,
this will disable interrupts from 7 + 1 cycles (7 + the
DISI instruction itself). In this case, the DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but the
DISI state machine does not properly re-engage
and continue to disable interrupts. At this point, all
interrupts are enabled. The next time the user code
executes a DISI instruction, the feature will act
normally and block interrupts.
In summary, it is only when DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Affected Silicon Revisions
A1
X
A2
X
6. Module: CPU
EXAMPLE 8:
LOOP1: MOV
LOOP0:
Note:
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT bit (CORCON<11>) will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C30 compiler.
Work around
The application should save the DCOUNT Special
Function Register (SFR) prior to entering the inner
DO loop and restore it upon exiting the inner DO
loop. This work around is shown in Example 8.
Affected Silicon Revisions
A1
X
.include “p30fxxxx.inc”
.......
DO #CNT1, LOOP0
....
PUSH DCOUNT
DO
....
BTSS Flag, #0
BSET CORCON, #EDT
....
....
POP
...
For details on the functionality of
EDT bit, see section 2.9.2.4
in the dsPIC30F Family Reference
Manual.
MOV W5, W8
A2
X
#CNT2, LOOP1
W1, W5
DCOUNT
SAVE AND RESTORE
DCOUNT
© 2010 Microchip Technology Inc.
;Outer loop start
;Save DCOUNT
;Inner loop
;starts
;Terminate inner
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends