PIC16LC926T-I/PT Microchip Technology, PIC16LC926T-I/PT Datasheet - Page 112
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PIC16LC926T-I/PT
Manufacturer Part Number
PIC16LC926T-I/PT
Description
IC MCU CMOS 20MHZ 8K W/LCD64TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC926T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
OTP
Ram Size
336 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
336 B
Interface Type
I2C, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC926T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16C925/926
12.7
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
(Section 12.1).
12.7.1
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
FIGURE 12-12:
FIGURE 12-13:
DS39544A-page 110
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
81h, 181h
Note: PSA and PS2:PS0 are bits in the OPTION register.
Address
2007h
DD
Watchdog Timer (WDT)
and process variations from part to part (see
by
WDT PERIOD
Config. bits
clearing
OPTION
Name
WATCHDOG TIMER BLOCK DIAGRAM
SUMMARY OF WATCHDOG TIMER REGISTERS
WDT Timer
Enable bit
WDT
configuration
RBPU
Bit 7
From TMR0 Clock Source
(Figure 5-6)
(1)
BOREN
INTEDG
bit
Bit 6
0
1
WDTE
(1)
PSA
M
U
X
Preliminary
T0CS
Bit 5
CP1
assigned to the WDT under software control, by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, prevent it
from timing out and generating a device RESET
condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
12.7.2
It should also be taken into account that under worst
case conditions (V
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
0
T0SE
Bit 4
Note:
CP0
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
PWRTE
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
WDT PROGRAMMING
CONSIDERATIONS
8
Bit 3
PSA
DD
(1)
PSA
To TMR0 (Figure 5-6)
= Min., Temperature = Max., and
WDTE
Bit 2
PS2
2001 Microchip Technology Inc.
PS2:PS0
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0