PIC18F2580-E/SO Microchip Technology, PIC18F2580-E/SO Datasheet - Page 383
PIC18F2580-E/SO
Manufacturer Part Number
PIC18F2580-E/SO
Description
IC PIC MCU FLASH 16KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F4480-IPT.pdf
(490 pages)
3.PIC18F4480-IPT.pdf
(8 pages)
4.PIC18F4480-IPT.pdf
(6 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18F2580-E/SO
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2580-E/SO
Manufacturer:
Microchi
Quantity:
2 952
- PIC18F2221-ISO PDF datasheet
- PIC18F4480-IPT PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F2580-ESO PDF datasheet #6
- Current page: 383 of 490
- Download datasheet (9Mb)
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Clear f
CLRF
0 ≤ f ≤ 255
a ∈ [0,1]
000h → f,
1 → Z
Z
Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
CLRF
Read
0110
Q2
=
=
f {,a}
5Ah
00h
101a
FLAG_REG,1
Process
Data
Q3
ffff
register ‘f’
PIC18F2480/2580/4480/4580
Write
Q4
ffff
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WDT Counter
WDT Counter
WDT Postscaler
TO
PD
Q1
operation
Clear Watchdog Timer
CLRWDT
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the post-
scaler of the WDT. Status bits TO and
PD are set.
1
1
CLRWDT
0000
No
Q2
=
=
=
=
=
0000
?
00h
0
1
1
Process
Data
Q3
DS39637D-page 383
0000
operation
No
Q4
0100
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