PIC18F242-E/SP Microchip Technology, PIC18F242-E/SP Datasheet - Page 139
PIC18F242-E/SP
Manufacturer Part Number
PIC18F242-E/SP
Description
IC MCU CMOS 40MHZ 8K FLASH 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
Specifications of PIC18F242-E/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F242-E/SP
Manufacturer:
Microchip Technology
Quantity:
135
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- Current page: 139 of 332
- Download datasheet (6Mb)
REGISTER 15-5:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: MSSP CONTROL REGISTER 2 (I
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
0 = Acknowledge sequence IDLE
RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I
0 = Receive IDLE
PEN: STOP Condition Enable bit (Master mode only)
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
RSEN: Repeated START Condition Enabled bit (Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins.
0 = Repeated START condition IDLE
SEN: START Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is enabled for slave transmit only (Legacy mode)
Legend:
R = Readable bit
- n = Value at POR
Note:
GCEN
R/W-0
Note:
Automatically cleared by hardware.
Automatically cleared by hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
ACKSTAT
R/W-0
ACKDT
R/W-0
W = Writable bit
’1’ = Bit is set
2
C
ACKEN
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
2
R/W-0
RCEN
C MODE)
R/W-0
2
PEN
C module is not in the IDLE
PIC18FXX2
x = Bit is unknown
R/W-0
RSEN
DS39564C-page 137
R/W-0
SEN
bit 0
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